UPD17015GS datasheet(85/120 Pages) NEC

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µPD17015

14.3.5

Cautions When Using Clock-Stop Instruction

The clock-stop instruction (STOP s instruction) is valid only when the CE pin is low level.

The program must take into account processing when the CE pin is raised unexpectedly to high level.

The description is based on the following example.

Example

XTAL

DAT

0000B

; Clock-stop condition symbol definition

CEJDG:

; 1

SKF1

; Built-in Macro

; Detects the CE pin input level.

MAIN

; If CE = high level, branches to main processing.

Process A

; CE = low level processing

; 2

STOP

XTAL

; Clock-stop

; 3

$–1

MAIN:

Main processing

CEJDG

In the example above, the state of the CE pin is detected at 1 . If the CE pin is low level, after process A is executed,

the clock-stop instruction “STOP XTAL” of 2 is executed.

However, if the CE pin becomes high level while the “STOP XTAL” instruction of 2 is being executed as shown

in the figure below, the “STOP XTAL” instruction operates as a no operation instruction (NOP).

If the branch instruction “BR $-1” of 3 does not exit, the program returns to main processing and erroneous

operational occurs.

Therefore, a branch instruction like 3 must be inserted in the program, or the program must be written so that

erroneous operational does not occur even if it returns to main processing.

When a branch instruction like 3 is used, CE reset is applied in synchronization with the next setting of the BTM0CY

flag, even if the CE pin remains at high level.

3.0 V

0 V

VDD

CE pin

STOP XTAL

The STOP XTAL

becomes a NOP

instruction because

the CE pin is high

level.

The program starts from

address 0 in synchronization

with setting of the BTM0CY

flag. (CE reset)

Main

proces-

sing

Process A

CE pin detection

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