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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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UPD17015GS Arkusz danych(PDF) 65 Page - NEC |
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UPD17015GS Arkusz danych(HTML) 65 Page - NEC |
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65 / 120 page  65 µPD17015 12. BEEP 12.1 CONFIGURATION AND FUNCTIONS Fig. 12-1 shows an overview of BEEP. A 3-kHz clock is output from the P0D0/BEEP pin. According to the settings of the BEEP0SEL flag of the LCD enable register, the output switching block controls whether the P0D0/BEEP pin functions as a general-purpose output port or as a BEEP output pin. The clock generation block generates the 3-kHz clock to be output to the BEEP pin. Fig. 12-2 shows the configuration and functions of the LCD enable register. Fig. 12-1 Overview of BEEP P0D 0/BEEP 3 kHz BEEP0SEL flag Output switching block Clock generation block Fig. 12-2 Configuration and Functions of the LCD Enable Register b 3 b 2 b 1 b 0 P 0 A B I O 0 P 0 A B I O 1 B E E P 0 S E L L C D E N 6AH R/W Read/write Address 0 00 00 00 00 1 CE Hold Clock-Stop Power-on Name Flag symbol LCD enable register Sets the function of the P0D0/BEEP pin. Uses the P0D0/BEEP pins as a general-purpose output port. Uses the P0D0/BEEP pin as a BEEP output pin. 4 |
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