Normal mode functionality

AN3090

6/19

Doc ID16496 Rev 1

2

Normal mode functionality

During normal operation, the serial data present on the SDI pin is transferred to the shift

register in synchronization with the CLK rising edge. After 16 CLK pulses, the data loaded

on the SDI pin is shifted to the SDO pin with a typical delay of 22 ns, as shown on the plot in

Figure 2.

This delay guarantees the correct synchronization of the CLK and SDI signals if two or more

STP16DPPS05 devices are cascaded.

Figure 2.

Typical data transfer from SDI to SDO

The data present in any register is transferred to the respective latch when the latch-enable

(LE/DM1) signal is high (serial-to-parallel conversion).

After this step, the data is transferred to the outputs via the output-enable pin (OE/DM2),

which turns on the LEDs at the current set by the external resistor.

By changing the OE/DM2 duty cycle, it is possible to set the output dimming if the

application requires slow or fast frame visualization.