Results

AN2267

10/19

5

Results

Experimental implementation of this scheme yielded satisfactory results. A closed loop

regulator for BLDC motor control with inner current and outer speed loops as shown in

Figure 10 was implemented. Current loop sampling time of 500µs and speed loop sampling

time of 2ms was chosen. The amount of computing time required within a 2ms time window

to execute through a full cycle of control loop and all motor control ISRs at an electrical

frequency of 200Hz is less than 1ms. The important waveforms obtained are shown in

figures 11 and 12. Figure 11 shows the convergence of reference and actual phase current

values at the instant of occurrence of U event which is the feedback sampling instant. Notice

that the U event occurs during the middle of PWM ON time. Figure 12 shows the tight

control of motor average phase current for a given current reference.

Figure 10.

Closed loop current and speed control - block diagram

Vdclink

BLDC

duty

-

+

-

+

Speed

estimator

ω

ω

I*

PI reg

PI reg

ST7FMC controller