AN2691

RPD functionality

3/10

Refer to the product documentation for a full description of the reset mechanism.

The RSTIN pin is an input of the device that can be configured as an output that shows a

low level during the internal reset condition. This is called bidirectional reset and is enabled

by setting the BDRSTEN bit in the SYSCON register.

When enabled, the open drain of the RSTIN pin is activated, pulling down the reset signal

for the duration of the internal reset sequence (synchronous/asynchronous hardware,

synchronous software and synchronous watchdog timer resets). At the end of the internal

reset sequence (1024 TCL) the pull-down is released.

The figure below shows a simplified reset circuitry scheme. Please refer to the product user

manual for more details and timings related to system reset.

Figure 1.

Internal (simplified) reset circuitry

RSTOUT

EINIT instruction

Trigger

Clr

Clock

Reset state

machine

Internal

reset

signal

Reset sequence

(512 CPU clock cycles)

SRST instruction

watchdog overflow

RSTIN

BDRSTEN

RPD

Weak pull-down

(–200 µA)

From/to exit

powerdown

circuit

Asynchronous

reset

Clr

Q

Set