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UPD703003 Arkusz danych(PDF) 23 Page - NEC |
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UPD703003 Arkusz danych(HTML) 23 Page - NEC |
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23 / 82 page ![]() 23 µPD703003 Data Sheet U12261EJ2V1DS00 The configurations of the timer/counter functions are shown below. Figure 8-1. Block Diagram of Timer 1 (16-bit timer/event counter) Notes 1. Internal count clock 2. External count clock 3. Priority to reset Remark φ : internal system clock n = 1 to 4 Figure 8-2. Block Diagram of Timer 4 (16-bit interval timer) Note Internal count clock Remark φ : Internal system clock m m/4 m/8 m/32 φ φ φ φ /2 /4 φ φ m φ TCLR1n TI1n INTP1n0 INTP1n1 INTP1n2 INTP1n3 Note 2 Note 1 Clear and start TM1n (16 bits) CC1n0 CC1n1 CC1n2 CC1n3 INTOV1n INTCC1n0 INTCC1n1 S R Note3 Q Q S Q Q R Note3 INTCC1n2 INTCC1n3 TO1n0 TO1n1 Edge detect Clear and start Edge detect Edge detect Edge detect Edge detect Edge detect TM4 (16-bit) CM4 Clear and start INTCM4 Note m m/32 φ φ m φ /2 /4 /16 /32 φ φ φ φ |
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