UPD703003 datasheet(60/82 Pages) NEC

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µPD703003

Data Sheet U12261EJ2V1DS00

(1) Clock timing

Parameter

Symbol

Conditions

25-MHz Version

33-MHz Version

Units

MIN.

MAX.

MIN.

MAX.

X1 input cycle

<1>

tCYX

Direct mode

Note 1

PLL mode (PLL locked)

200

250

150

250

X1 input high-level width

<2>

tWXH

Direct mode

PLL mode

X1 input low-level width

<3>

tWXL

Direct mode

PLL mode

X1 input rise time

<4>

tXR

Direct mode

PLL mode

X1 input fall time

<5>

tXF

Direct mode

PLL mode

CPU operating frequency

—

Direct mode

Note 2

MHz

PLL mode

Note 3

MHz

CLKOUT output cycle

<6>

tCYK

Note 4

CLKOUT input high-level width

<7>

tWKH

0.5T – 5

CLKOUT input low-level width

<8>

tWKL

0.5T – 5

CLKOUT input rise time

<9>

tKR

CLKOUT input fall time

<10> tKF

↓ → CLKOUT delay time

<11> tDXK

Direct mode

Notes 1. When using A/D converter

: 100 ns

When not using A/D converter

: DC

2. When using A/D converter

: 5 MHz

When not using A/D converter

: 0 MHz

3. Free-running oscillation frequency

4. When using A/D converter

: 200 ns

When not using A/D converter

: DC

Remark T = tCYK

Parameter

Symbol

Conditions

TYP.

Units

Free-running oscillation frequency

—

φP

PLL mode

MHz

X1 (input)

CLKOUT (output)

<1>

<2>

<4>

<5>

<6>

<7>

<11>

<8>

<9>

<10>

<3>

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