M24M02-DRMN6TP datasheet(36/38 Pages) STMICROELECTRONICS

36 / 38 page

Revision history

M24M02-DR

36/38

DocID18204 Rev 8

Revision history

Table 18. Document revision history

Date

Revision

Changes

22-Dec-2010

Initial release.

09-Feb-2011

Updated:

– Section 3.18: Read Identification Page

– Section 3.19: Read the lock status

– Figure 2: SO8 connections

– Table 6: Absolute maximum ratings

– Table 10: Input parameters

– Table 11: DC characteristics

– Table 12: AC characteristics at 400 kHz

– Table 13: 1 MHz AC characteristics

Deleted:

– Table 15 “Available M24M02-x products (package, voltage range,

frequency, temperature grade)”.

09-Aug-2011

Updated Figure 5: Maximum Rbus value versus bus parasitic

capacitance (Cbus) for an I2C bus at maximum frequency fC = 1 MHz

and Table 11: DC characteristics.

07-Feb-2012

Updated:

– Table 2: Device select code

– Table 3: Most significant address byte

– Table 4: Least significant address byte.

– Section 3.6: Write operations

– Section 3.8: Page Write

25-Oct-2012

Updated document template and text (minor changes).

Cycling updated to 4 million cycles and data retention updated to

200 years.

Added WLCSP packages.

04-Jun-2013

Document reformatted.

Removed information related to thin WLCSP package.

Updated:

– WLCSP package silhouette on cover page

– Section 1: Description

– Figure 3: WLCSP connections

– Note (1) under Table 6: Absolute maximum ratings.

Added Figure 18: WLCSP- 8-bump, 3.556 x 2.011 mm, wafer level

chip scale package recommended footprint

M24M02-DRMN6TP Arkusz danych(PDF) 36 Page - STMicroelectronics

M24M02-DRMN6TP Arkusz danych(HTML) 36 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Arkusz danych Pobierz

Link URL