AD7993 datasheet(13/27 Pages) AD

13 / 27 page

AD7994/AD7993

–13–

REV. PrF

PRELIMINARYTECHNICAL DATA

CIRCUIT INFORMATION

The AD7994/AD7993 are fast, low-power, 12-/10-bit,

single supply, 4 Channel A/D converters respectively. The

parts can be operated from a 2.7 V to 5.5 V supply.

The AD7994/AD7993 provide the user with a 4-channel

multiplexer, an on-chip track/hold, A/D converter, an on-

chip oscillator, internal data registers and an I

2C compat-

ible serial interface, all housed in a 16-lead TSSOP

package, which offers the user considerable space saving

advantages over alternative solutions. An external reference

is required by the AD7994/AD7993, and this reference can

be in the range of 1.2 V to VDD.

The AD7994/AD7993 will normally remain in a power-

down state while not converting. When supplies are first

applied the part will come up in a shutdown state. Power-

up is intitiated prior to a conversion and the device returns

to power-down upon completion of the conversion. Con-

versions can be initiated on the AD7994/AD7993 by either

pulsing the

CONVST signal, using an automatic cycling

mode or using a mode where wake-up and conversion oc-

cur during the write function ( see modes of Operation

section). On completion of a conversion the AD7994/

AD7993 will enter shutdown mode again. This automatic

shutdown feature allows power saving between conversions.

This means any read or write operations across the I

interface can occur while the device is in shut-down.

ADC TRANSFER FUNCTION

The output coding of the AD7994/AD7993 is straight

binary. The designed code transitions occur at successive

integer LSB values (i.e., 1LSB, 2LSBs, etc.). The LSB

size for the AD7994 is = REFIN/4096 and REFIN/256 for

the AD7993 . The ideal transfer characteristic for the

AD7994/AD7993 is shown in Figure 4 below.

CONVERTER OPERATION

The AD7994/AD7993 are successive approximation ana-

log-to-digital converters based around a capacitive DAC.

Figures 2 and 3 show simplified schematics of the ADC

during its acquisition and conversion phase respectively.

Figure 2 shows the ADC during its acquisition phase.

SW2 is closed and SW1 is in position A, the comparator

is held in a balanced condition and the sampling capacitor

acquires the signal on VINX.

When the ADC starts a conversion, see Figure 3, SW2

will open and SW1 will move to position B causing the

comparator to become unbalanced. The input is discon-

nected once the conversion begins. The Control Logic

and the Capacitive DAC are used to add and subtract

fixed amounts of charge from the sampling capacitor to

bring the comparator back into a balanced condition.

When the comparator is rebalanced the conversion is com-

plete. The Control Logic generates the ADC output code.

Figure 4 shows the ADC transfer function.

Figure 2. ADC Acquisition Phase

Figure 3. ADC Conversion Phase

Figure 4. AD7994/AD7993 Transfer Characteristic

TYPICAL CONNECTION DIAGRAM

Figure 5 shows the typical connection diagram for the

AD7994/AD7993. In Figure 5 the Address Select pin,

AS, is tied to VDD, however AS can also be either tied to

GND or left floating, allowing the user to select up to

three AD7994/AD7993 devices on the same serial bus. An

external reference must be applied to the AD7994/

AD7993. This reference can be in the range of 1.2 V to

VDD. A precision reference like the REF 19X family,

ADR421, ADR03, ADR381 can be used to supply the

Reference Voltage to the ADC.

SDA and SCL form the two-wire I2C/SMBus compatible

interface. External Pull-up resistors should be added to

the SDA and SCL bus lines.

The AD7994-0/AD7993-0 support Standard and Fast I

Interface Modes. While the AD7994-1/AD7993-1 support

Standard, Fast and High-speed I

2C Interface Modes.

Therefore if operating the AD7994/AD7993 in either

Standard or Fast Mode, up to five AD7994/AD7993 de-

vices (3 x AD7994-0/AD7993-0 and 2 x AD7994-1/

AD7993-1 or 3 x AD7994-1/AD7993-1 and 2 x AD7994-

0/AD7993-0) can be connected to the bus. When operat-

ing in Hs-Mode then up to three AD7994-1/AD7993-1

devices can be connected to the bus.

Wake-up from power-down prior to a conversion is ap-

proximately 1µs while conversion time is approximately

2µs. The AD7994/AD7993 enters power-down mode

again after each conversion, this will be useful in applica-

tions where power consumption is of concern.

CAPACITIVE

DAC

V IN

COMPARATOR

CONTROL

LOGIC

SW1

SW2

AGND

CAPACITIVE

DAC

V IN

COMPARATOR

CONTROL

LOGIC

SW1

SW2

AGND

000...000

ANALOG INPUT

0 V TO REFIN

111...111

000...001

000...010

111...110

111...000

011...111

AGND +1 LSB

+REFIN -1LSB

AD7994 1 LSB = REFIN/4096

AD7993 1 LSB = REFIN/256

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