AD7993 datasheet(27/27 Pages) AD

27 / 27 page

AD7994/AD7993

–27–

REV. PrF

PRELIMINARYTECHNICAL DATA

16-Lead TSSOP (RU-16)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

0.201 (5.10)

0.193 (4.90)

SEATING

PLANE

0.006 (0.15)

0.002 (0.05)

0.0118 (0.30)

0.0075 (0.19)

0.0256

(0.65)

BSC

0.0433

(1.10)

MAX

0.0079 (0.20)

0.0035 (0.090)

0.028 (0.70)

0.020 (0.50)

8°

0°

It is recommended that no I

2C Bus activity occurs when a

conversion is taking place. However if this is not possible,

e.g. when operating in Mode 2 or Mode 3, then in order

to maintain the performance of the ADC, Bits D7 and D6

in the Cycle Timer Register are used to delay critical

sample intervals and bit trials from occurring while there

is activity on the I

2C Bus. This will result in a quiet pe-

riod for each bit decision. In certain cases where there is

excessive activity on the interface lines this may have the

effect of increasing the overall Conversion time. However

if bit trial delays extend longer than 1 µs the conversion

will terminate.

When bits D7 and D6 are both 0, the bit trial and sample

interval delaying mechanism will be implemented. The

default setting of D7 and D6 is 0. To turn off both set D7

and D6 to 1.

Sample Bit Trial 0

Cyc

Dealy

Delay

Bit2

Bit1

Bit0

Cycle Timer Register

*Default settings at Power-up

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