AD7994/AD7993

–17–

REV. PrF

PRELIMINARYTECHNICAL DATA

CONVERSION RESULT REGISTER

The Conversion Result Register is a 16-bit read-only reg-

ister which stores the conversion result from the ADC in

Straight Binary format. A Two Byte read is necessary to

read data from this register. Table VIIa shows the contents

of the first byte to be read while Table VIIb show the

contents of the second byte to be read from AD7994/

AD7993.

The AD7994/AD7993 conversion result consists of an

Alert_Flag bit, a leading zero, two Channel Identifier bits

and the 12-/10- bit data result. For the AD7993 the two

LSBs (D1 and D0) of the second read will contain two

zeros.

The Alert_Flag bit indicates whether the conversion result

being read or any other channel result has violated the

limit registers associated with it. The Master may wish to

read the ALERT Status register to obtain more informa-

tion on where the ALERT occurred if this Alert_Flag bit

is set.

This is followed by a leading zero and the two Channel

Indentifier bits indicating which channel the conversion

result corresponds to. The 12-/10-bit conversion result

then follows MSB first.

Table VI. ALERT/BUSY Function

D2

D1

ALERT/BUSY Pin Configuration

0

0

Pin does not provide any interrupt signal.

0

1

Pin configured as a BUSY output.

1

0

Pin configured as an ALERT output.

1

1

Resets ALERT output pin, Alert_Flag bit in

Conversion Result Reg, and entire Alert

Status Reg ( if any active).

Note 1:- The AD7994/AD7994 converts on the selected channel in the Sequence in ascending order, starting with the

lowest channel in the sequence.

Table V. Channel Selection

D7

D6

D5

D4

Analog Input Channel

0

0

0

0

No channel selected, see Address Pointer Byte, Mode 2

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

Alert_Flag

1

Zero

Channel# Result

0/1

0

0

0

0/1

0

0

1

0/1

0

1

0

0/1

0

1

1

Table VIIb.

Conversion Value Register (Second Read)

D7

D6

D5

D4

D3

D2

D1

D0

B7

B6

B5

B4

B3

B2

B1/0

B0/0

Table VIIa.

Conversion Value Register (First Read)

D15

D14

D13

D12

D11

D10

D9

D8

M S B B10

B9

B8

If 1/1 is written to bits D2/D1 in the configuration Regis-

ter to reset the ALERT pin, the Alert Flag bit and the

Alert Status Register; the contents of the Configuration

Register will read 1/0 for D2/D1 respectively if read back.