8

HV311

VDD

UV

OV

VEE SENSE GATE

RAMP

HV311

-48V

R4

12.5mΩ

R1

487kΩ

R2

6.81kΩ

R3

9.76kΩ

Q1

IRF530

C

LOAD

+5.0V

8

3

2

COM

1

GND

C1

10nF

+

-

DC/DC

PWM

CONVERTER

PWRGD

ENABLE

5

7

4

6

VDD

UV

OV

VEE SENSE GATE

RAMP

HV311

PWRGD

-48V

Cload

+5.0V

8

3

2

5

7

4

COM

1

GND

+

-

DC/DC

PWM

CONVERTER

ENABLE

R4

12.5mΩ

R1

487kΩ

R2

6.81kΩ

R3

9.76kΩ

Q1

IRF530

C1

10nF

6

Application Circuit 1

Application Circuit 2

Note:

A capacitor may be needed to slow PWRGD dv/dt if gate oscillations are observed when V

Note:

A capacitor may be needed to slow PWRGD dv/dt if gate oscillations are observed when V

PWRGD Output

Many DC/DC PWM converters reference their ENABLE inputs to the negative input terminal. If the ENABLE input is active

LOW then the HV311 can be directly connected as shown below

(Application Circuit 1) since the open drain PWRGD out-

put is in a High-Z state until the external MOSFET is fully turned on and the potential on the negative input of the converter

is essentially the same as the VEE pin of the HV311.

However, if the DC/DC PWM Converter with the ENABLE input circuit configuration was active HIGH, then the apparent

choice of the HV311 would result in the creation of a current path through the protective diode clamp of the ENABLE input

and the PWRGD output MOSFET of the HV311. For this situation the HV311 should be used as shown below.