HV311_09 datasheet(6/17 Pages) SUTEX

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HV311

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A numerical example:

CL = 50mV

CB = 100mV

CS = 10mΩ

MAX · RCS = VCL

CB · RCS = VCB

MAX = 5.0A

CB = 10A

Timing

The ﬁgure shows the sequence of events during startup

and associated timing characteristics. The following is a dis-

cussion of timing values assuming the following component

values:

RAMP = 10nF

LOAD = 100μF

VDD = 48V

MOSFET = IRF530

GS(TH) = 3.0V

m = 7.4S

CS = 50mΩ (IMAX = 1.0A)

•

A number of false starts may be caused by contact bounce

at the card edge. The startup begins when V

VIN rises through

the lower enable voltage V

LEN, whose level is programmed at

the UV comparator.

START

During this time the RAMP voltage rises steadily as the 10μA

current source charges capacitor C

RAMP. The voltage at the

GATE pin starts to follow the RAMP pin voltage when V

RAMP

reaches a ﬁxed offset voltage V

OFS of about 1.2V after a de-

lay indicated as t

START in the ﬁgure.

START · IRAMP = VOFS · CRAMP

START = (1.2)(10n)/(10μ)

START = 1.2ms

This time interval is associated with the rise of the GATE

voltage from zero to the gate threshold voltage of the exter-

nal MOSFET.

TH · IRAMP = VGS(TH) · CRAMP

TH = (3)(10n)/(10μ)

START = 3.0ms

RISE

During this time period the drain current rises more or less

exponentially to the maximum inrush current I

MAX. As current

rises from zero, the RAMP current is reduced by the action

of the current sense ampliﬁer, hence the more or less expo-

nential current rise. t

RISE is here deﬁned as the time to reach

90% of I

MAX.

90% rise corresponds to 2.3τ

RAMP · τ = CRAMP · ΔVGS

MAX ≈ gm · ΔVGS

RISE ≈ 2.3(CRAMP · IMAX) / (IRAMP · gm)

RISE ≈ (2.3)(10n)(1)/(10μ)(7.4) = 0.3ms

LIM

During this time period the external load capacitor is charged

at I

MAX.

MAX · tLIM = CLOAD · VVDD

LIM = (100μ)(48) / (1)

LIM = 4.8ms

PWRGD

Final rise of GATE voltage to V

REG minus about 1.2V.

RAMP · tPWRGD = CRAMP · (VREG – (1.2V + VGS(TH) + ΔVGS))

PWRGD = (10n)(10 – (1.2 + 3 + 1/7.4)/(10μ)

PWRGD = 4.3ms

•

Design Information (cont.)

GND

-48V

VIN

IIN

tSTART

contact

bounce

ILIM

PWRGD

VUVL

tRISE

tPWRGD

VGATE

Initialization

Limiting

Full On

VGATE

VOUT

tLIM

tTH

VRAMP

RAMP

GATE

inactive

active

OUT

VGS(th)

VGS(lim)

VEE

tPOR

90%

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