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VDP3108 Arkusz danych(PDF) 33 Page - Micronas

Numer części VDP3108
Szczegółowy opis  Single-Chip Video Processor
PDF  61 Pages
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Producent  MICRONAS [Micronas]
Strona internetowa  http://www.micronas.com
Logo MICRONAS - Micronas

VDP3108 Arkusz danych(HTML) 33 Page - Micronas

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ADVANCE INFORMATION
VDP 3108
MICRONAS INTERMETALL
33
Name
Default
Function
FP Sub
address
FP Display Control Register, BCL
h’d4
BCL threshold current, 0..2047 (max ADC output ~1152)
1000
BCLTHR
h’d2
BCL time constant. 0..15 ––> 0.5 .. 100msec
15
BCLTM
h’d3
BCL loop gain. 0..1023. Bit 11 must be always set to 1.
0
BCLG
h’d5
BCL minimum contrast. 0..1023
307
BCLMIN
h’75
Test register for BCL/EHT comp. function, register value:
1
stop ADC offset compensation
x>1
use x in place of input from Measurement ADC
0
BCLTST
FP Display Control Register, Deflection
h’73
interlace offset, –2048..2047
this value is added to the SAWTOOTH output during one field
0
INTLC
h’72
discharge sample count for deflection retrace,
SAWTOOTH DAC output impedance is reduced for DSCC lines after
vertical retrace.
7
DSCC
h’8f
vertical discharge value,
SAWTOOTH output value during discharge operation, typically same as
A0 init value for sawtooth
–1365
DSCV
h’7b
EHT (electronic high tension) compensation coefficient. 0..1023
0
EHT
h’7a
EHT time constant. 0..15 ––> 0.5 .. 100msec
15
EHTTM
FP Display Control Register, Vertical Sawtooth
h’80
DC offset of SAWTOOTH output,
this offset is independent of EHT compensation.
0
OFS
h’8b
accu0 init value
–1365
A0
h’8c
accu1 init value
900
A1
h’8d
accu2 init value
0
A2
h’8e
accu3 init value
0
A3
FP Display Control Register, East–West Parabola
h’9b
accu0 init value
–1121
A0
h’9c
accu1 init value
219
A1
h’9d
accu2 init value
479
A2
h’9e
accu3 init value
–1416
A3
h’9f
accu4 init value
1052
A4
1) The white drive values will become active only after writing the blue value WDB, latching of new values is indicated
by setting the MSB of WDB.



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