VDP3108 datasheet(39/61 Pages) MICRONAS

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ADVANCE INFORMATION

VDP 3108

MICRONAS INTERMETALL

age is generated by a 4 bit R-DAC and uses digital noise

shaping.

Pin 37 – DAC Reference Decoupling/Beam Current

Safety VRD/BCS (Fig. 4–13)

Via this pin the DAC reference voltage is decoupled by

an external capacitance. The DAC output currents de-

pend on this voltage, therefore a pulldown transistor can

be used to shut off all beam currents. A decoupling ca-

pacitor of 3.3

µF//100nF is required.

Pin 39 – Supply Voltage, Analog Backend VSUPO

Pin 40, 42, 44 – Analog RGB Output

ROUT, GOUT,

BOUT (Fig. 4–14)

This are the analog Red/Green/Blue outputs of the back-

end. The outputs sink a current of max. 8mA.

Pin 41, 47, 50 – Ground, Analog Backend GNDO

Pin 43 – Fast Blank Input FBLIN (Fig. 4–12)

This pin is used to switch the RGB outputs to the external

analog RGB inputs.

Pin 45, 51–53 – not connected

Pin 46 – Measurement ADC Input SENSE (Fig. 4–12)

This is the input of the analog digital converter for the

picture and tube measurement.

Pin 48,49 – Range Switch for Meas. ADC, RSW, RSW2

(Fig. 4–9)

These pins are open drain pulldown outputs. RSW is

switched off during cutoff and whitedrive measurement.

RSW2 is switched off during cutoff measurement only.

Pin 54, 60 – Supply Voltage, Clk20 Output VSUPB,

Ground Clk20 Output GNDB.

Pin 55 – Main Clock Output Clk20 (Fig. 4–7)

This is the 20.25 main system clock, that is used by all

circuits in a high-end VDP system. All external timing is

derived from this clock.

Pin 56 – Supply Voltage, Analog Frontend VSUPI

Pin 57 – Chroma Input CIN (Fig. 4–15)

This pin is connected to the S-VHS chroma signal. A re-

sistive divider is used to bias the input signal to the

middle of the converter input range. CIN can only be

connected to the chroma (Video 2) AD converter. The

signal must be AC-coupled.

Pin 58 – Ground, Analog Frontend GNDF

Pin 59,61,63 – Video Input 1–3 VIN1,VIN2,VIN3

(Fig. 4–16)

These are the analog video inputs. A CVBS or S-VHS

luma signal is converted using the luma (Video 1) AD

converter. The VIN1 input can also be switched to the

chroma (Video 2) ADC. The input signal must be AC-

coupled.

Pin 60 – Ground, Clock 20 Buffer, GNDB

Pin 62 – Reference Voltage Top VRT (Fig. 4–17)

Via this pin, the reference voltage for the AD converters

is decoupled. The pin is connected with 10

µF//47 nF to

the Signal Ground Pin.

Pin 64 – Signal Ground for Analog Input ISGND

This is the high quality ground reference for the video

input signals.

Pin 65 – Horizontal Flyback Input HFLB (Fig. 4–12)

This pin is connected to the horizontal flyback pulse from

the horizontal deflection stage. This flyback pulse is

used for synchronization of the display processor and for

generation of the display clock.

Pin 66 – Safety Input SAFETY (Fig. 4–12)

Pin 67 – Vertical Protection Input VPROT (Fig. 4–12)

The vertical protection circuitry prevents the picture tube

from burn-in in the event of a malfunction of the vertical

deflection stage. During vertical blanking, a signal level

of 2.5V is sensed. If a negative edge cannot be detected,

the RGB output signals are blanked.

Pin 68 – Front Sync Pulse FSY (Fig. 4–8)

This pin supplies the front sync information.

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