WM8944BECSSLASHR datasheet(90/165 Pages) CIRRUS

90 / 165 page

WM8944B

Rev 4.3

The GPIO inputs to the Interrupt Controller are de-bounced to avoid false detections. The timeout

clock (TOCLK) is required for this function. When using GPIO inputs to the Interrupt Controller, the

TOCLK must be enabled by setting the TOCLK_ENA and OSC_CLK_ENA bits as described in

“Clocking and Sample Rates”.

The Interrupt (IRQ) output can be globally masked by setting the IM_IRQ register. The Interrupt is

masked by default.

The Interrupt (IRQ) output may be configured on any of the GPIO pins

. See “General Purpose Input /

Output” for details of how to configure GPIO pins for Interrupt (IRQ) output.

The Interrupt control fields are defined in Table 63.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R16 (10h)

System

Interrupts

(Read only)

TEMP_INT

Thermal Interrupt status (Read only)

0 = Thermal interrupt not set

1 = Thermal interrupt set

This bit is latched when set; it is cleared

when the register is Read.

GP2_INT

GPIO2 Interrupt status (Read only)

0 = GPIO2 interrupt not set

1 = GPIO2 interrupt set

This bit is latched when set; it is cleared

when the register is Read.

GP1_INT

GPIO1 Interrupt status (Read only)

0 = GPIO1 interrupt not set

1 = GPIO1 interrupt set

This bit is latched when set; it is cleared

when the register is Read.

LDO_UV_INT

LDO Undervoltage Interrupt (Read only)

0 = LDO Undervoltage interrupt not set

1 = LDO Undervoltage interrupt set

This bit is latched when set; it is cleared

when the register is Read.

R18 (12h)

IRQ Config

IM_IRQ

IRQ (GPIO output) Mask

0 = Normal

1 = IRQ output is masked

R19 (13h)

System

Interrupts

Mask

IM_TEMP_INT

Interrupt mask for thermal status

0 = Not masked

1 = Masked

IM_GP2_INT

Interrupt mask for GPIO2

0 = Not masked

1 = Masked

IM_GP1_INT

Interrupt mask for GPIO1

0 = Not masked

1 = Masked

IM_LDO_UV_IN

Interrupt mask for LDO Undervoltage

status

0 = Not masked

1 = Masked

Table 63 Interrupt Control

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