WM8944BECSSLASHR datasheet(95/165 Pages) CIRRUS

95 / 165 page

WM8944B

Rev 4.3

R/W

A14

A13

A12

SDA

SCLK

15-bit control register address

16-bit control register data

B15

B14

B13

Figure 41 3-Wire Serial Control Interface

POWER MANAGEMENT

The WM8944B has two control registers that allow users to select which functions are active. For

minimum power consumption, unused functions should be disabled. To minimise pop or click noise, it

is important to enable or disable these functions in the correct order, and to use the signal mute

registers as part of a carefully structured control sequence.

The power management control registers are described in Table 67.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R2 (02h)

Power

management

INPGA_ENA

Input PGA Enable

0 = Disabled

1 = Enabled

ADCR_ENA

Right ADC Enable

0 = Disabled

1 = Enabled

ADCR_ENA must be set to 1 when

processing right channel data from

the Digital Microphone.

ADCL_ENA

Left ADC Enable

0 = Disabled

1 = Enabled

ADCL_ENA must be set to 1 when

processing data from the ADC or

from the Left Digital Microphone.

MICB_ENA

Microphone Bias Enable

0 = Disabled

1 = Enabled

BIAS_ENA

Master Bias Enable

0 = Disabled

1 = Enabled

R3 (03h)

Power

management

OUT_ENA

LINEOUT enable

0 = Disabled

1 = Enabled

SPK_PGA_ENA

Speaker PGA enable

0 = Disabled

1 = Enabled

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