WM8944BECSSLASHR datasheet(93/165 Pages) CIRRUS

93 / 165 page

WM8944B

Rev 4.3

device ID

B15

data bits B15

– B8

ACK

R/W

(Read)

data bits B15

– B8

ACK

STOP

ACK

A15

SDA

SCLK

device ID

Note: The SDA pin is driven by both the master and slave devices in turn to transfer device address, register address, data and ACK responses

R/W

– A8

START

(Write)

ACK

Rpt

START

– A0

Figure 35 Control Interface 2-wire (I2C) Register Read

The Control Interface also supports other register operations, as listed above. The interface protocol

for these operations is summarised below. The terminology used in the following figures is detailed in

Table 66.

Note that, for multiple write and multiple read operations, the auto-increment option must be enabled.

This feature is enabled by default, as noted in Table 65.

TERMINOLOGY

DESCRIPTION

Start Condition

Repeated start

Acknowledge (SDA Low)

¯¯

Not Acknowledge (SDA High)

Stop Condition

R/W

¯¯

ReadNotWrite

0 = Write

1 = Read

[White field]

Data flow from bus master to WM8944B

[Grey field]

Data flow from WM8944B to bus master

Table 66 Control Interface Terminology

Device ID

MSByte Address

(0)

MSByte Data

LSByte Data

8 bit Device ID

8 bits

LSByte Address

8 bits

Figure 36 Single Register Write to Specified Address

Device ID

MSByte Data

(1)

LSByte Data

Device ID

MSByte Address

(0)

LSByte Address

Figure 37 Single Register Read from Specified Address

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