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WM8944BECS/R Arkusz danych(PDF) 27 Page - Cirrus Logic

Numer części WM8944BECS/R
Szczegółowy opis  Mono Low-Power CODEC with Video Buffer
PDF  165 Pages
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Producent  CIRRUS [Cirrus Logic]
Strona internetowa  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8944BECS/R Arkusz danych(HTML) 27 Page - Cirrus Logic

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WM8944B
Rev 4.3
27
DMICCLK pin
DMICDAT pin
(Left/Right channels
interleaved)
1
2
1
2
1
2
MIC1 output
(Left Channel)
1
1
1
MIC2 output
(Right Channel)
2
2
2
hi-Z
Figure 10 Digital Microphone Interface Timing
The digital microphone interface control fields are described in Table 6.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R2 (02h)
Power
Management 1
7
DMIC_ENA
0
Enables Digital Microphone mode
0 = Audio DSP input is from ADC
1 = Audio DSP input is from digital
microphone interface
When DMIC_ENA = 0, the Digital
microphone clock (DMICCLK) is
held low.
Table 6 Digital Microphone Interface Control
ANALOGUE-TO-DIGITAL CONVERTER (ADC)
The WM8944B uses a 24-bit sigma-delta ADC. The use of multi-bit feedback and high oversampling
rates reduces the effects of jitter and high frequency noise. The ADC full-scale input level is
proportional to LDOVOUT
. See “Electrical Characteristics” section for further details. Any input signal
greater than full scale may overload the ADC and cause distortion.
The ADC and associated digital record filters are enabled by the ADCL_ENA register bit.
The ADC digital blocks are also required for the digital microphone interface; the Left and Right digital
microphone paths are enabled by ADCL_ENA and ADCR_ENA respectively.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R2 (02h)
Power
Management
1
11
ADCR_ENA
0
Right ADC Enable
0 = Disabled
1 = Enabled
ADCR_ENA must be set to 1 when
processing right channel data from
the Digital Microphone.
10
ADCL_ENA
0
Left ADC Enable
0 = Disabled
1 = Enabled
ADCL_ENA must be set to 1 when
processing data from the ADC or
from the Left Digital Microphone.
Table 7 ADC Enable Control



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