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STM32F303VC Arkusz danych(PDF) 92 Page - STMicroelectronics |
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STM32F303VC Arkusz danych(HTML) 92 Page - STMicroelectronics |
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92 / 148 page ![]() Electrical characteristics STM32F303xB STM32F303xC 92/148 DocID023353 Rev 13 Figure 24. Recommended NRST pin protection 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 57. Otherwise the reset will not be taken into account by the device. 6.3.16 Timer characteristics The parameters given in Table 58 are guaranteed by design. Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 58. TIMx(1)(2) characteristics 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 and TIM17 timers. 2. Guaranteed by design. Symbol Parameter Conditions Min Max Unit tres(TIM) Timer resolution time -1 - tTIMxCLK fTIMxCLK = 72 MHz 13.9 - ns fTIMxCLK = 144 MHz x=1.8 6.95 - ns fEXT Timer external clock frequency on CH1 to CH4 -0 fTIMxCLK/2 MHz fTIMxCLK = 72 MHz 0 36 MHz ResTIM Timer resolution TIMx (except TIM2) - 16 bit TIM2 - 32 tCOUNTER 16-bit counter clock period - 1 65536 tTIMxCLK fTIMxCLK = 72 MHz 0.0139 910 µs fTIMxCLK = 144 MHz x=1.8 0.0069 455 µs tMAX_COUNT Maximum possible count with 32-bit counter - - 65536 × 65536 tTIMxCLK fTIMxCLK = 72 MHz - 59.65 s fTIMxCLK = 144 MHz x=1.8 - 29.825 s |
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