MAS3587F datasheet(37/82 Pages) MICRONAS

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ADVANCE INFORMATION

MAS 3587F

Micronas

D0:7f3

Oscillator Frequency (reset = 18432dec)

All

bit[19:0]

oscillator frequency in kHz

In order to achieve a correct internal operating frequency of the DSP, the nom-

inal crystal frequency has to be deposited into this memory cell.

Changes at this memory address must be validated by setting bit 0 of D0:7f1.

OfreqControl

D0:7f4

Output Clock Configuration (pin CLKO) (reset = 80000hex)

All

bit[19]

CLKO configuration

output clock signal at CLKO

1 (reset)

CLKO is tristate

The CLKO output pin of the MAS 3587F can be disabled via bit [19].

bit[18]

Reserved, must be set to zero

bit[17]

Additional division by 2 if scaler is on (bit[8] cleared)

0 (reset)

oversampling factor 512/768

oversampling factor 256/384

bit[16:9]

Reserved, must be set to zero

bit[8]

Output clock scaler

0 (reset)

set output clock according to audio sample rate

(see Table 2–1)

output clock fixed at 24.576 or 22.5792 MHz

For a list of output frequencies at pin CLKO please refer to Table 2–1.

bit[7:0]

reserved, must be set to zero

Changes at this memory address must be validated by setting bit[0] of D0:7f1.

OutClkConfig

D0:7f8

S/PDIF1) channel status bits category code setting (reset = 8004hex) All

SpdOutBits

D0:7f9

Soft Mute (reset = 0hex)

Decoder

bit[19:0]

0 (reset)

mute off

mute on

SoftMute

D0:7fc

Volume output control: left

→ left gain (reset = 80000

hex)

Decoder

out_LL

D0:7fd

Volume output control: left

→ right gain (reset = 0

hex)

Decoder

out_LR

D0:7fe

Volume output control: right

→ left gain(reset = 0

hex)

Decoder

out_RL

D0:7ff

Volume control: right

→ right gain (reset = 80000

hex)

Decoder

out_RR

1) IEC 958 Amendment1, “Digital Audio Interface”

Table 3–7: D0 Control Memory Cells

Memory

Address

(hex)

Function

Name

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