MAS3587F datasheet(11/82 Pages) MICRONAS

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ADVANCE INFORMATION

MAS 3587F

Micronas

2.8.1. DSP Clock

The DSP clock has a separate divider. For power con-

servation it is set to the lowest acceptable rate of the

synthesizer clock which is capable to allow the proces-

sor core to perform all tasks.

2.8.2. Clock Output at CLKO

If the DSP or audio codec functions are enabled (bits

11 or 10 in the Control Register at I2C subaddress

6ahex), the reference clock at pin CLKO is derived from

the synthesizer clock.

Dependent on the sample rate of the decoded signal a

scaler is applied which automatically divides the clock-

out by 1, 2, or 4, as shown in Table 2–1. An additional

division by 2 may be selected by setting bit 17 of the

Output Clock Configuration memory cell, OutClkConfig

(see Table 3–7 on page 34). The scaler can be dis-

abled by setting bit 8 of this cell.

The controlling at OutClkConfig is only possible as

long as the DSP is operational (bit 10 of the Control

by clearing bit 10.

2.9. Power Supply Concept

The MAS 3587F has been designed for minimal power

dissipation. In order to optimize the battery manage-

ment in portable players, two DC/DC converters have

been implemented to supply the complete portable

audio player with regulated voltages.

2.9.1. Power Supply Regions

The MAS 3587F has five power supply regions.

The VDD/VSS pin pair supplies all digital parts includ-

ing the DSP core, the XVDD/XVSS pin pair is con-

nected to the digital signal pin output buffers, the

AVDD0/AVSS0 supply is for the analog output amplifi-

ers, AVDD1/AVSS1 for all other analog circuits like

clock oscillator, PLL circuits, system clock synthesizer

and A/D and D/A converters. The I2C interface has an

own supply region via pin I2CVDD. Connecting this to

the microcontroller supply assures that the I2C bus

always works as long as the microcontroller is alive so

that the operating modes can be selected.

Beside these regions, the DC/DC converters have

start-up circuits of their own which get their power via

pin VSENSx.

2.9.2. DC/DC Converters

The MAS 3587F has two embedded high-performance

step-up DC/DC converters with synchronous rectifiers

to supply both the DSP core itself and external circuitry

such as a controller or flash memory at two different

voltage levels. An overview is given in Fig. 2–7 on

page 12.

The DC/DC converters are designed to generate an

output voltage between 2.0 V and 3.5 V which can be

programmed separately for each converter via the I2C

interface (see Table 3–3 on page 20). Both converters

are of the bootstrapped type which allow start up from

a voltage down to 0.9 V for use with a single battery or

NiCd/NiMH cell. The default output voltages are 3.0 V.

Both converters are enabled with a high level at pin

DCEN and enabled/disabled by the I2C interface.

The MAS 3587F DC/DC converters feature a constant-

frequency, low noise pulse width modulation (PWM)

mode and a low quiescent current, pulse frequency

modulation (PFM) mode for improved efficiencies at

low current loads. Both modes – PWM or PFM – can

be selected independently for each converter via I2C

interface. The default mode is PWM.

In the PWM mode, the switching frequency of the

power-MOSFET-switches is derived from the crystal

oscillator. Switching harmonics generated by constant

frequency operation are consistent and predictable.

When the audio codec is enabled the switching fre-

quency of the converters is synchronised to the audio

codec clock to avoid interferences into the audio band.

The actual switching frequency can be selected via the

I2C-interface between 300 kHz and 580 kHz (for

details see DCFR Register in Table 3–3 on page 20).

In the PFM operation mode, the switching frequency is

controlled by the converters themself, it will be just

high enough to service the output load thus resulting in

the best possible efficiency at low current loads. PFM

mode does not need a clock signal from the crystal

oscillator. If both converters do not use the PWM-

mode, the crystal clock will be shut down as long it is

not needed from other internal blocks.

The synchronous rectifier bypasses the external

Schottky diode to reduce losses caused by the diode

forward voltage providing up to 5% efficiency improve-

ment. By default, the P-channel synchronous rectifier

switch is turned on when the voltage at pin(s) DCSOn

exceeds the converter’s output voltage at pin(s)

VSENSn and turns off when the inductor current drops

below a threshold. If one or both converters are dis-

abled, the corresponding P-channel switch will be

turned on, connecting the battery voltage to the DC/

DC converters output voltage at pin VSENSn. How-

ever, it is possible to individually disable both synchro-

nous rectifier switches by setting the corresponding

bits (bit 8 and 0 in DCCF-register).

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