LTC4221IGN datasheet(8/28 Pages) LINER

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LTC4221

4221f

PI FU CTIO S

ON1 (Pin 1): System/Channel 1 On Input. Both GATE pins

are pulled low by internal 100µA pull-downs and the

FAULT latch is reset when VON1 < 0.4V. When 0.425V <

VON1 < 0.821V, the FAULT latch is released from reset.

When VON1 > 0.851V, GATE1 ramps up after an initial

timing cycle.

VCC1 (Pin 2): Channel 1 Positive Supply Input. It powers

all the internal circuitry. VCC1 can range from 2.7V to 13.5V

for normal operation but it must be ≥VCC2. An undervolt-

age lockout circuit disables both channels whenever the

voltage at VCC1 is less than 2.5V.

SENSE1 (Pin 3): Channel 1 Current Sense Input. A sense

resistor RSENSE1 is placed in the supply path between VCC1

and SENSE1 to sense channel 1 load current. If VRSENSE1

exceeds 100mV for more than 1µs or 25mV for an adjust-

able time (set by the CFILTER), the FAULT latch is set and

fast pull-down circuits are triggered to discharge both

GATEs low. During the start-up cycle, GATE1 ramp-up is

controlled to servo VRSENSE1 ≤ VSENSE(ACL). VSENSE(ACL)

increases from 9mV to 25mV as VFB1 ramps from 0V to

0.5V. To disable the current limit and circuit breaker

function for channel 1, tie SENSE1 to VCC1.

GATE1 (Pin 4): Channel 1 Gate Drive. This pin is the high

side gate drive of an external N-channel MOSFET. When

VON1 < 0.821V, GATE1 is held low by a 100µA current

source. When VON1 > 0.851V, an initial timing cycle is

followed by a start-up cycle when an internal charge pump

provides a 9.5µA pull-up to ramp up GATE1 with inrush

current limiting. UVLO, overvoltage, overcurrent and ex-

ternally generated faults override the ON1 pin and pull

GATE1 low.

FB1 (Pin 5): VOUT1 Feedback Input. FB1 monitors the

channel 1 output voltage with an external resistive divider.

When VFB1 < 0.617V, the PWRGD1pin is pulled low. When

VFB1 > 0.822V, overvoltage is detected, the FAULT latch is

set and both GATEs are pulled low. The FB1pin is also used

to control the channel 1 current limit during its start-up

cycle.

PWRGD1 (Pin 6): Channel 1 Power Good Output. PWRGD1

is pulled low when VFB1 < 0.617V, during the initial timing

cycle or when the chip is in UVLO. An external pull-up is

required to generate a logic high at the open-drain PWRGD1

pin.

TYPICAL PERFOR A CE CHARACTERISTICS

VPWRGD(OL)/VFAULT(OL)

vs Temperature

tp(SC-FAULT) vs Temperature

TEMPERATURE (°C)

–50

0.500

0.450

0.400

0.350

0.300

0.250

0.200

0.150

0.100

0.050

4221 G37

–25

100

125

VCC1 = 2.7V

VCC1 = 5V

VCC1 = 13.5V

VCC2 = 1V, IPWRGD/IFAULT = 1.6mA

TEMPERATURE (°C)

–50

4221 G38

–25

100

125

VCC1 = 2.7V

VCC1 = 5V

VCC1 = 13.5V

VCC2 = 1V

TIMER = 0.5V

TEMPERATURE (°C)

–50

1.4

1.6

1.8

4221 G39

1.2

1.0

–25

100

125

0.8

0.6

VCC1 = 2.7V

VCC1 = 5V

VCC1 = 13.5V

VCC2 = 1V

TIMER = 0.5V

tp(FC-GATE) vs Temperature

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