LTC4221IGN datasheet(13/28 Pages) LINER

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LTC4221

4221f

APPLICATIO S I FOR ATIO

Undervoltage Lockout

An internal undervoltage lockout (UVLO) occurs if either

VCC supply is too low for normal operation. The LTC4221

is kept in lockout mode in which the internal charge pumps

are off, the GATE pins, TIMER are held low by internal

N-channel MOSFET pull-downs and the FAULT latch reset,

cutting off both channels. VCC1 has a low-to-high UVLO

threshold of 2.5V with 110mV hysteresis. VCC2 has a low-

to-high UVLO threshold of 0.8V with 25mV hysteresis.

Both UVLOs have glitch filters that filter out dips that are

less than 30µs, allowing for bus supply transients. An

additional requirement for normal operation is VCC1 ≥

VCC2.

ON Pin Functions

The ON1 pin serves as a global reset for the LTC4221. It

has an internal reset comparator with a high-to-low thresh-

old of 0.4V, a 25mV hysteresis and a high-to-low glitch

filter of 15µs. Pulling ON1 below this threshold will put the

LTC4221 into a reset state in which the TIMER is pulled low

by an internal N-channel MOSFET pull-down, the GATE

pins are pulled low by separate internal 100µA pull-downs

and the FAULT latch resets. A low-to-high transition on the

ON1 pin past the reset threshold releases the reset on the

FAULT latch and both channels go into an off state.

In addition to its global reset function, ON1 also serves as

an on/off switch for channel 1. ON2 performs the same

role for channel 2. Both pins have an off comparator with

a high-to-low threshold of 0.821V and 30mV hysteresis.

With these, ON1 and ON2 can be used to force a simulta-

neous or sequential power-up/power-down of the two

channels. A simultaneous power-up and power-down is

shown in Figure 2b. Both VCC pins clear their respective

UVLO at time point 1 and both channels enter reset state.

When ON1 clears its reset threshold, either ON1 or ON2

clears its off threshold, both GATEs < 0.4V and TIMER <

0.4V (time point 2), an initial timing cycle starts. At time

point 4, the initial timing cycle completes and the LTC4221

checks that FILTER is low and FAULT is high. If both

conditions are met, it then monitors the voltage of ON1 and

ON2. As long as its ON pin has cleared its off threshold,

each channel powers up regardless of the state of the other

channel. Similarly, if its ON pin goes below its off thresh-

old, each channel pulls its GATE pin down with an internal

100µA pull-down and turns off its external MOSFET re-

gardless of the state of the other channel. As the circuit in

Figure 2a has its two ON pins shorted together, a simulta-

neous power-up is programmed at time points 4 to 5 and

a simultaneous power down is programmed between time

points 7 and 8. The timing waveforms in Figure 3 show a

VCC1

ON1

SENSE1

ON2

RF2

15k

LTC4221*

GATE1

FB1

4221 F02a

4221 F02b

CTIMER

1µF

GND

TIMER

(2a) Circuit

(2b) Timing Waveforms

RF1

56k

VOUT1

3.3V

VOUT2

2.5V

IRF7413

RSENSE1

0.004Ω

CLOAD1

Z1 = SMAJ10

* ADDITIONAL DETAILS

OMITTED FOR CLARITY

RX1

10Ω

CX1

100nF

10k

LONG

VCC1

LONG

PCB EDGE

CONNECTOR

(MALE)

SHORT

BACKPLANE

CONNECTOR

(FEMALE)

LONG

VCC2

DISCHARGE

BY LOAD

VCCn

VOUTn

GATE

UVLO

INITIAL

TIMING

CHANNEL

START-UP

RESET STATE

TIMER

0.851V

1.234V

0.821V

9.5µA

100µA

VTH

20µA

23 4

5 6

7 8

NORMAL

RESET

VCCn(UVL)

1.9µA

Figure 2. Simultaneous Power On/Off

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