LTC4221IGN datasheet(15/28 Pages) LINER

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LTC4221

4221f

generate a logic high output to indicate that VOUT is valid.

An internal high-to-low glitch filter helps to prevent nega-

tive voltage transients on each FB pin from deasserting its

PWRGD. The relationship between glitch filter time and an

FB pin transient voltage is shown in Figure 4. Using the

functionality of the PWRGD1 pin, the LTC4221 can be

configured to do sequential power-up and power-down as

shown by the circuit in Figure 5. Referring back to Figure 3,

ON2 is held low until VOUT1 ramps high enough for FB1 to

exceed its undervoltage threshold at time point 5 when

PWRGD1 ramps up, pulling ON2 high. At time point 7, the

control logic sees ON2 exceeding its off threshold and so

commences a start-up cycle for channel 2. Similarly, when

ON1 is forced low by Q2 at time point 9, GATE1 is pulled

low by its 100µA pull-down while ON2 is held high by the

R4 pull-up on PWRGD1. Its is only when channel 1 is

powered off and VOUT1 discharges below its undervoltage

threshold at time point 10 that PWRGD1’s internal

N-channel MOSFET pull-down is triggered and ON2 goes

low. At time point 11, ON2 trips its off threshold and

GATE2 pulls low with a 100µA pull-down, powering off

channel 2.

For VOUT overvoltage detection, each FB pin has an over-

voltage comparator with a low-to-high threshold of 0.822V

and a low-to-high glitch filter of 18µs. This threshold is

designed to be 33% higher than the undervoltage thresh-

old. If either FB pin trips this threshold, the fault latch is set,

all GATE pins are pulled low with internal NFET pull-downs

and the LTC4221 goes into a fault state.

In the third function, each FB pin is used to control its

channel’s current limit during its start-up cycle. This will

be featured in the Start-Up Cycle with Current Limit

section.

GATE Pin Functions

Each GATE pin controls the gate of its channel’s external

N-channel MOSFET. Individual internal charge pumps

and maximum 18V (internally clamped) for GATE1 and

GATE2. During UVLO, the internal charge pumps are off

and both GATE pins are pulled low by internal N-channel

MOSFET pull-downs. Outside UVLO, when ON1 is below

its off threshold, the charge pumps are on and GATE1 is

held low by an internal 100µA current pull-down. Once

APPLICATIO S I FOR ATIO

VCC1

ON1

SENSE1

ON2

PWRGD1

RF2

15k

LTC4221*

GATE1

FB1

4221 F05

CTIMER

1µF

GND

TIMER

RF1

56k

VOUT1

3.3V

VOUT2

2.5V

IRF7413

RSENSE1

0.004Ω

CLOAD1

Q2: 2N7002LT1

Z1: SMAJ10

* ADDITIONAL DETAILS

OMITTED FOR CLARITY

RX1

10Ω

CX1

100nF

10k

R5 10Ω

R3 10k

LONG

VCC1

LONG

PCB EDGE

CONNECTOR

(MALE)

SHORT

BACKPLANE

CONNECTOR

(FEMALE)

LONG

VCC2

ON/OFF

Figure 5. Using PWRGD1 to Configure Sequential Power-Up/Power-Down

FEEDBACK TRANSIENT (mV)

20 40 60 80 100 120 140 160 180 200

4221 F04

TA = 25°C

Figure 4. FB Comparator Glitch Filter

Time vs Feedback Transient Voltage

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