LPC47M14X datasheet(60/205 Pages) SMSC

60 / 205 page

SMSC DS – LPC47M14X

Page 60

Rev. 05/02/2000

ENHANCED DUMPREG

The DUMPREG command is designed to support system run-time diagnostics and application software development

and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the eighth

byte of the DUMPREG command has been modified to contain the additional data from these two commands.

COMPATIBILITY

The LPC47M14x was designed with software compatibility in mind. It is a fully backwards- compatible solution with the

older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as

well as PC/AT and PC/XT, floppy disk controller subsystems. After a hardware reset of the FDC, all registers, functions

and enhancements default to a PC/AT, PS/2 or PS/2 Model 30 compatible operating mode, depending on how the

IDENT and MFM bits are configured by the system BIOS.

6.6

SERIAL PORT (UART)

The LPC47M14x incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE

registers and the NS16C550A. The UARTs perform serial-to-parallel conversion on received characters and parallel-to-

serial conversion on transmit characters. The data rates are independently programmable from 460.8K baud down to

50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and

prioritized interrupts. The UARTs each contain a programmable baud rate generator that is capable of dividing the input

clock or crystal by a number from 1 to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to

the Configuration Registers for information on disabling, power down and changing the base address of the UARTs.

The interrupt from a UART is enabled by programming OUT2 of that UART to a logic "1". OUT2 being a logic "0"

disables that UARTs interrupt. The second UART also supports IrDA, HP-SIR and ASK-IR modes of operation.

Note: The UARTs 1 and 2 may be configured to share an interrupt. Refer to the Configuration section for more

information.

Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial ports are

defined by the configuration registers (see “Configuration” section). The Serial Port registers are located at sequentially

increasing addresses above these base addresses. The LPC47M14x contains two serial ports, each of which contain a

Table 29 – Addressing the Serial Port

DLAB*

Receive Buffer (read)

Transmit Buffer (write)

Interrupt Enable (read/write)

Interrupt Identification (read)

FIFO Control (write)

Line Control (read/write)

Modem Control (read/write)

Line Status (read/write)

Modem Status (read/write)

Scratchpad (read/write)

Divisor LSB (read/write)

Divisor MSB (read/write

*Note: DLAB is Bit 7 of the Line Control Register

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