LPC47M14X datasheet(85/205 Pages) SMSC

85 / 205 page

SMSC DS – LPC47M14X

Page 85

Rev. 03/19/2001

ECP IMPLEMENTATION STANDARD

This specification describes the standard interface to the Extended Capabilities Port (ECP). All LPC devices supporting

ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a

description of the ECP Protocol, please refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface

Standard, Rev. 1.14, July 14, 1993. This document is available from Microsoft.

Description

The port is software and hardware compatible with existing parallel ports so that it may be used as a standard LPT port if

ECP is not required. The port is designed to be simple and requires a small number of gates to implement. It does not

do any "protocol" negotiation, rather it provides an automatic high burst-bandwidth channel that supports DMA for ECP

in both the forward and reverse directions.

Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the maximum

bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic handshake for the

standard parallel port to improve compatibility mode transfer speed.

The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is

accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is

to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of

times. Hardware support for compression is optional.

Table 42 – ECP Pin Descriptions

NAME

TYPE

DESCRIPTION

nStrobe

During write operations nStrobe registers data or address into the slave on

the asserting edge (handshakes with Busy).

PData 7:0

I/O

Contains address or data or RLE data.

nAck

Indicates valid data driven by the peripheral when asserted. This signal

handshakes with nAutoFd in reverse.

PeriphAck (Busy)

This signal deasserts to indicate that the peripheral can accept data. This

signal handshakes with nStrobe in the forward direction. In the reverse

direction this signal indicates whether the data lines contain ECP

command information or data. The peripheral uses this signal to flow

control in the forward direction. It is an "interlocked" handshake with

nStrobe. PeriphAck also provides command information in the reverse

direction.

PError

(nAckReverse)

Used to acknowledge a change in the direction the transfer (asserted =

forward).

The peripheral drives this signal low to acknowledge

nReverseRequest. It is an "interlocked" handshake with nReverseRequest.

The host relies upon nAckReverse to determine when it is permitted to

drive the data bus.

Select

Indicates printer on line.

nAutoFd

(HostAck)

Requests a byte of data from the peripheral when asserted, handshaking

with nAck in the reverse direction. In the forward direction this signal

indicates whether the data lines contain ECP address or data. The host

drives this signal to flow control in the reverse direction. It is an

"interlocked" handshake with nAck. HostAck also provides command

information in the forward phase.

nFault

(nPeriphRequest)

Generates an error interrupt when asserted. This signal provides a

mechanism for peer-to-peer communication. This signal is valid only in the

forward direction. During ECP Mode the peripheral is permitted (but not

required) to drive this pin low to request a reverse transfer. The request is

merely a "hint" to the host; the host has ultimate control over the transfer

direction. This signal would be typically used to generate an interrupt to

the host CPU.

nInit

Sets the transfer direction (asserted = reverse, deasserted = forward).

This pin is driven low to place the channel in the reverse direction. The

peripheral is only allowed to drive the bi-directional data bus while in ECP

Mode and HostAck is low and nSelectIn is high.

nSelectIn

Always deasserted in ECP mode.

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