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RA4M3 Arkusz danych(PDF) 55 Page - Renesas Technology Corp

Numer części RA4M3
Szczegółowy opis  Armv8-M architecture with the main extension
PDF  92 Pages
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Producent  RENESAS [Renesas Technology Corp]
Strona internetowa  http://www.renesas.com
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RA4M3 Arkusz danych(HTML) 55 Page - Renesas Technology Corp

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2.3.11
IIC Timing
Table 2.29
IIC timing (1) (1 of 2)
(1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B,
SCL0_B, SDA1_B, SCL1_B.
(2) The following pins do not require setting: SCL0_A, SDA0_A, SCL1_A, SDA1_A.
(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the
AC portion of the electrical characteristics is measured for each group.
Parameter
Symbol
Min
Max
Unit
Test
conditions
IIC
(Standard mode,
SMBus)
ICFER.FMPE = 0
SCL input cycle time
tSCL
6 (12) × tIICcyc + 1300
ns
Figure 2.43
SCL input high pulse width
tSCLH
3 (6) × tIICcyc + 300
ns
SCL input low pulse width
tSCLL
3 (6) × tIICcyc + 300
ns
SCL, SDA rise time
tSr
1000
ns
SCL, SDA fall time
tSf
300
ns
SCL, SDA input spike pulse
removal time
tSP
0
1 (4) × tIICcyc ns
SDA input bus free time when
wakeup function is disabled
tBUF
3 (6) × tIICcyc + 300
ns
SDA input bus free time when
wakeup function is enabled
tBUF
3 (6) × tIICcyc + 4 × tPcyc +
300
ns
START condition input hold time
when wakeup function is disabled
tSTAH
tIICcyc + 300
ns
START condition input hold time
when wakeup function is enabled
tSTAH
1 (5) × tIICcyc + tPcyc + 300
ns
Repeated START condition input
setup time
tSTAS
1000
ns
STOP condition input setup time
tSTOS
1000
ns
Data input setup time
tSDAS
tIICcyc + 50
ns
Data input hold time
tSDAH
0
ns
SCL, SDA capacitive load
Cb
400
pF
RA4M3 Datasheet
2. Electrical Characteristics
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 55 of 92



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