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STM32L010F4 Arkusz danych(PDF) 40 Page - STMicroelectronics |
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STM32L010F4 Arkusz danych(HTML) 40 Page - STMicroelectronics |
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40 / 91 page ![]() Electrical characteristics STM32L010F4/K4 40/91 DS12323 Rev 3 6.3 Operating conditions 6.3.1 General operating conditions 6.3.2 Embedded reset and power control block characteristics The parameters given in the following table are derived from the tests performed under the ambient temperature condition summarized in Table 15. Table 15. General operating conditions Symbol Parameter Conditions Min Max Unit fHCLK Internal AHB clock frequency - 0 32 MHz fPCLK1 Internal APB1 clock frequency - 0 32 fPCLK2 Internal APB2 clock frequency - 0 32 VDD Standard operating voltage - 1.8 3.6 V VDDA Analog operating voltage (all features) Must be the same voltage as VDD(1) 1.8 3.6 V VIN Input voltage on FT and RST pins(2) 2.0 V ≤ VDD ≤ 3.6 V –0.3 5.5 V 1.8 V ≤ VDD ≤ 2.0 V –0.3 5.2 Input voltage on BOOT0 pin - 0 5.5 Input voltage on TC pin - –0.3 VDD+ 0.3 PD Power dissipation at TA = 85 °C(3) TSSOP20/ LQFP32 - 270/ 333 mW TA Temperature range - –40 85 °C TJ Junction temperature range (range 6) –40 °C ≤ TA ≤ 85 ° –40 105 1. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and normal operation. 2. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled. 3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 14: Thermal characteristics on page 39). Table 16. Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit tVDD(1) VDD rise time rate BOR detector enabled 0 - ∞ µs/V BOR detector disabled 0 - 1000 VDD fall time rate BOR detector enabled 20 - ∞ BOR detector disabled 0 - 1000 TRSTTEMPO(1) Reset temporization VDD rising, BOR enabled - 2 3.3 ms |
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