LTC3312SAAVPBF datasheet(10/28 Pages) AD

10 / 28 page

LTC3312SA

Rev. 0

For more information www.analog.com

PIN FUNCTIONS

SSTT1 (Pin 1) : Soft-Start, Tracking, Temperature Monitor

Input for Buck Regulator 1. An internal 4µA current into

an external capacitor on the soft-start pin programs the

output voltage ramp rate during start-up. When SSTT1 is

below 0.5V, the FB1 pin voltage will track the SSTT1 pin

voltage. When SSTT1 is above 0.5V, the tracking function

is disabled, the internal reference resumes control of the

error amplifier and the SSTT1 pin servos to a voltage

proportional to junction temperature. For a clean recov-

ery from an output short circuit condition, the SSTT1

pin is pulled down to approximately 100mV above the

VFB voltage and a new soft-start cycle is initiated. During

shutdown and fault conditions, the SSTT1 pin is pulled to

ground. Short the SSTT1 pin to AVIN to use an internally

set default soft-start time of 1ms (typical).

FB1 (Pin 2): Feedback Input for Buck Regulator 1.

Program the output voltage of Buck 1 by connecting this

pin to the middle node of a resistor divider between the

output and ground. The FB1 pin is regulated to 500mV. A

phase lead capacitor connected between VOUT1 and FB1

may be used to optimize transient response.

EN1 (Pin 3): Active High Enable Input for Buck Regulator 1.

The EN1 pin has a precision threshold. An external resistor

divider from VIN, or from another supply, can be used to

program when Buck Regulator 1 is enabled. If the enable

function is not required, tie EN1 directly to AVIN. The EN1

pin should not be floated.

PGOOD1 (Pin 4): Power Good (Open-Drain) Output for

Buck Regulator 1. When the regulated output voltage

is outside the power-good voltage window, and PVIN is

above 2.25V, this pin is driven LOW. The PGOOD1 output

is also pulled low when PVIN is above 2.25V and Buck

Regulator 1 is in shutdown.

SW1 (Pins 5, 6): Switch Node for Buck Regulator 1.

Connect an external inductor to this pin.

PVIN1 (Pins 7, 8): Input Supply for Buck Regulator 1.

Supplies gate drive circuits and inductor current when

the high side turns on. Bypass PVIN1 to PGND with a

separate low ESR capacitor close to the pins. PVIN1 and

PVIN2 should be shorted externally. Use separate capaci-

tors to PGND for PVIN1 and PVIN2 to prevent interaction

between the buck regulators. There is an internal 20Ω

resistor from PVIN1 to AVIN to help create a filtered supply

for the internal control circuits.

PGND (Pins 9,10, 23): The PGND pins are the return path

of the internal bottom side power switches. Connect the

PGND pins together and to the exposed pad. Connect

the negative terminal of the input capacitors as close to

the PGND pins as possible. The PGND node is the main

thermal highway and should be connected to a large PCB

ground plane with many large vias.

PVIN2 (Pins 11, 12): Input Supply for Buck Regulator 2.

Supplies gate drive circuits and inductor current when

the high side turns on. Bypass PVIN2 to PGND with a

separate low ESR capacitor close to the pins. PVIN1 and

PVIN2 should be shorted externally. Use separate capaci-

tors to PGND for PVIN1 and PVIN2 to prevent interaction

between the buck regulators. There is an internal 20Ω

resistor from PVIN2 to AVIN to help create a filtered supply

for the internal control circuits.

SW2 (Pins 13,14): Switch Node for Buck Regulator 2.

Connect an external inductor to this pin.

MODE/SYNC (Pin 15): Mode Selection and External Clock

Synchronization Input. Ground this pin to enable pulse-

skipping mode. Tie this pin to AVIN to enable Burst Mode

operation for higher efficiency at light loads. Float this

pin to enable forced continuous mode for fast transient

response and full frequency operation over a wide load

range. Drive MODE/SYNC with an external clock to syn-

chronize both switchers to the applied frequency. The

slope compensation is automatically adapted to the exter-

nal clock frequency. In the absence of an external clock,

the RT pin controls the switching frequency.

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