LTC3312SAAVPBF datasheet(13/28 Pages) AD

13 / 28 page

LTC3312SA

Rev. 0

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OPERATION

Dual Buck Switching Regulators

The LTC3312SA is a 5V dual 6A monolithic, constant fre-

quency, peak current mode step-down DC/DC converter.

The synchronous buck switching regulators are internally

compensated and require only external feedback resistors

to set the output voltage.

An internal oscillator, with frequency set using a resis-

tor on the RT pin or synchronized to an external clock,

turns on the internal top power switch at the start of each

clock cycle, (the clock’s rising edge for Buck 1). Current

in the inductor then increases until the top switch current

comparator trips and turns off the top power switch. The

peak inductor current at which the top switch turns off

is controlled by an internal VC voltage. The error ampli-

fier regulates VC by comparing the voltage on the FB pin

with an internal 500mV reference. When the load current

increases it causes a reduction in the feedback voltage

relative to the reference leading the error amplifier to raise

the VC voltage until the average inductor current matches

the new load current. When the top power switch turns

off, the synchronous power switch turns on and ramps

down the inductor current for the remainder of the clock

cycle or, if in pulse-skipping or Burst Mode operation, until

the inductor current falls to zero. If overload conditions

result in excessive current flowing through the bottom

switch, the next clock cycle will be skipped until the switch

current returns to a safe level. The top switches of the two

buck regulators are turned on 180 degrees out of phase

to reduce input current ripple.

Each buck switching regulator has its own SW, FB, SSTT,

PGOOD, and EN pins. The enable pins have precision

400mV thresholds which may be used to provide event-

based power-up sequencing by connecting the enable pin

to the output of another buck through a resistor divider.

If the EN pin of a buck is low, that buck is in shutdown

and in a low quiescent current state. If both EN pins are

low, both bucks are in shutdown, the SW pins are high

impedance, and the quiescent current of the LTC3312SA

is 1.4µA (typical). If either EN pin is above the enable

threshold of 400mV, its respective buck is enabled.

Both buck regulators have forward and reverse current

limiting, short-circuit protection, output overvoltage pro-

tection, and soft-start to limit inrush current during start-

up or recovery from a short-circuit.

2-Phase, Single Output Operation

The LTC3312SA is easily configured as a single output,

2-phase, 12A buck regulator by connecting the FB2 and

SSTT2 pins to AVIN, and connecting the EN2 pin to AGND.

The PGOOD2 pin can be floated or shorted to ground. The

EN1 pin will control the enable for both power stages, and

the PGOOD1 pin functions as the power good indicator.

The part detects that FB2 is connected high and uses the

output of the error amplifier (VC) for Buck 1 to control the

peak inductor current for both buck power stages. The top

switches of the two phases are turned on 180 degrees

out of phase to reduce input current ripple. The differ-

ence between peak inductor currents of the two phases

are determined by internal matching and will typically be

within 10% of each other at high currents.

The equations used to determine the inductor value for a

single-phase 6A buck are also used to select the induc-

tors for the dual-phase 12A circuit (see Applications

Information section for inductor selection). The total

capacitance on the 2-phase output should be double what

is calculated for a single phase 6A buck (see Applications

Information section for output capacitor selection).

When waking up from sleep in Burst Mode operation,

the top switches of the two phases are turned on initially

without a delay, to improve the transient response coming

out of sleep. The 180-degree phase difference will start

on the subsequent turn-on after exiting sleep.

Input Supply

The AVIN pin is a noise-filtered version of PVIN used to

bias the internal bandgap reference and buck control cir-

cuits. A 1µF external filter capacitor should be connected

from AVIN to AGND, and no current should be drawn by

external circuits. AVIN connects to the PVIN1 and PVIN2

pins through internal 20Ω filter resistors.

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