LTC3312SAAVPBF datasheet(20/28 Pages) AD

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LTC3312SA

Rev. 0

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feedforward capacitor CFF placed between VOUT and FB.

Capacitor CFF provides phase lead compensation by cre-

ating a high frequency zero which improves the phase

margin and the high frequency response. The values used

in the typical application circuits are good starting points.

LTpowerCAD® is a useful tool to help optimize CFF and

COUT for a desired transient performance.

Applying a load transient and monitoring the response of

the system or using a network analyzer to measure the

actual loop response are two ways to experimentally verify

transient performance and control loop stability, and to

optimize CFF and COUT.

When using the load transient response method to sta-

bilize the control loop, apply an output current pulse of

20% to 100% of full load current having a very fast rise

time. This will produce a transient on the output voltage.

Monitor VOUT for overshoot or ringing that would indicate

a stability problem (see Application Note AN149).

Output Voltage Sensing

The LTC3312SA’s AGND pin is the ground reference for

the internal analog circuitry, including the bandgap voltage

reference. For the single output, 2-phase application, load

regulation can be improved by connecting the AGND pin

to the negative terminal of the output capacitor (COUT) at

the load. Any drop in the high current power ground return

path will be compensated. All of the signal components,

such as the FB resistor dividers and the RT resistor, should

be referenced to the AGND node. AGND carries very little

current and, therefore, can be a minimal size trace.

For dual-buck applications, connect the FB resistor divid-

ers, the RT resistor ground, and the AVIN capacitor ground

to the AGND pin close to the part. Connect AGND, using a

via, to a low resistance ground plane that minimizes any

voltage drops between AGND and the negative terminals

of the buck output capacitors.

Enable Threshold Programming

The LTC3312SA has precision threshold enable pins for

each buck regulator to enable or disable each buck. When

both are forced low, the device enters into a low current

shutdown mode.

The rising threshold of both EN comparators is 400mV,

with 50mV of hysteresis. The EN pins can be tied to AVIN

if the shutdown feature is not used. Adding a resistor

divider from PVIN to an EN pin programs the LTC3312SA

to regulate that output only when PVIN is above a desired

voltage. Typically, this threshold, VIN(EN), is used in situ-

ations where the input supply is current limited or has

a relatively high source resistance. A switching regula-

tor draws near constant power from its input source, so

source current increases as source voltage drops. This

looks like a negative resistance load to the source and can

cause the source to current limit or latch low under low

source voltage conditions. The VIN(EN) threshold prevents

the regulator from operating at source voltages where

problems may occur. Referring to Figure 2, this threshold

can be adjusted by setting the values R1 and R2 such that

they satisfy Equation 10.

PVIN EN

( ) =

+ 1

⎛

⎝⎜

⎞

⎠⎟

• 400mV

(10)

PVIN

3312SA F02

BUCK

SWITCHING

REGULATOR

Figure 2. EN Divider

The buck regulator will remain off until PVIN is above

PVIN(EN). The buck regulator will remain enabled until

PVIN falls to 0.875 • PVIN(EN) and EN is 350mV.

Alternatively, a resistor divider from the output of one

buck to the EN pin of the second buck provides event-

based power-up sequencing, as the first buck reaching

regulation enables the second buck. Replace PVIN(EN) in

Equation 10 with the desired output voltage of the first

buck, (e.g., 90% of the regulated value), at which the

second buck is enabled.

Output Voltage Tracking and Soft-Start

Each buck regulator has an independent SSTT pin. An

internal 4µA current pulls up each SSTT pin when that

buck is enabled, allowing an external capacitor from

APPLICATIONS INFORMATION

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