LTC3312SAAVPBF datasheet(22/28 Pages) AD

22 / 28 page

LTC3312SA

Rev. 0

For more information www.analog.com

and follow the recommendations below to ensure proper

operation. See Figure 5 for a recommended PCB layout.

3312SA F05

GND PLANE ON LAYER 2

GND

VOUT2

VOUT1

COUT1

COUT2

CIN1

CIN2

CFF1

CFF2

RB1

RA1

RA2 RB2

CVIN

VIN

Figure 5. Recommended PCB Layout

1. Connect the exposed pad of the package (Pin 23)

directly to a large, unbroken ground plane under the

application circuit on the layer closest to the surface

layer to minimize thermal and electrical impedance.

Additionally, short the exposed pad to pins 9 and 10 on

the top layer. See the Analog Devices Application Note,

Application Notes for Thermally Enhanced Leaded

Plastic Packages for the proper size and layout of the

thermal vias and solder stencils.

2. The PVIN1 (Pins 7, 8) and PVIN2 (Pins 11, 12) input

supply pins should have local decoupling capacitors

with the ground side of the capacitors connected on

the top layer to the ground plane close to pin 9 and

pin 10. These capacitors provide the AC current to

the internal power MOSFETs and their drivers. Large,

switched currents flow in these capacitors and it is

important to minimize inductance from these capaci-

tors by choosing a small case size, such as 0603, and

placing them close to the pins on the top side of the

board. To further minimize inductance and input noise,

smaller 0201 capacitors can be placed in parallel, also

as close as possible to the pins, from PVIN1 to PGND

and from PVIN2 to PGND.

3. Place both regulator inductors on the same side of the

board as the LTC3312SA. The switching power traces

connecting SW1 and SW2 to their inductors should be

minimized to reduce radiated EMI and parasitic cou-

pling. Due to the large voltage swing on the switching

nodes, high impedance sensitive nodes, such as the

feedback nodes, should be kept far away or shielded

from SW1 (Pins 5, 6) and SW2 (Pins 13, 14). Minimize

the trace lengths from the inductors to their output

capacitors.

4. Connect the ground side of any FB, RT, and SSTT com-

ponents to AGND (Pin 20). Connect a 1µF decoupling

capacitor from AVIN (Pin 21) to AGND, close to the

pins. For all layouts, only connect AGND to the rest of

the PCB ground plane in one location, to prevent tran-

sient currents in the ground plane from also flowing

through the AGND trace, which would cause voltage

noise between AGND referenced circuits.

For dual-buck applications, connect the AGND pin to

the ground plane with a single via, close to the AGND

pin. Use an unbroken low resistance ground plane to

minimize any voltage drops between AGND and the

negative terminals of the output capacitors.

For 2-phase, single output designs, optionally con-

nect the AGND pin to the negative terminal of the out-

put capacitor (COUT) at the load. This will reduce any

load regulation caused by voltage drops between the

ground at the load and the LTC3312SA voltage refer-

ence ground. The AGND node carries very little current

and, therefore, can be a minimal size trace. The ground

side of any FB, RT, and SSTT components, and the AVIN

capacitor ground should connect to the AGND node.

APPLICATIONS INFORMATION

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