LTC3312SAAVPBF datasheet(23/28 Pages) AD

23 / 28 page

LTC3312SA

Rev. 0

For more information www.analog.com

High Temperature Considerations

Care should be taken in the layout of the PCB to ensure

good heat sinking of the LTC3312SA. Connect the

exposed pad on the bottom of the package to a large

unbroken ground plane under the application circuit on

the layer closest to the surface layer. Place many vias to

minimize thermal and electrical impedance. Solder the

PGND pins directly to a ground plane on the top layer.

Connect the top layer ground plane to ground plane(s)

on lower levels with many thermal vias. These layers will

spread heat dissipated by the LTC3312SA. Figure 6 is a

simplified thermal representation of a thermally enhanced

LQFN package with exposed pad, with the silicon die and

thermal metrics identified. The current source represents

power loss PD on the die; node voltages represent tem-

peratures; electrical impedances represent conductive

thermal impedances θJCBOTTOM, θJCTOP, θVIA, θCB, and

convective thermal impedances θBA and θCA. The junction

temperature, TJ, is calculated from the ambient tempera-

ture, TA, as given by Equation 14.

TJ = TA +PD • θJA

(14)

where, neglecting the θJCTOP + θCA path.

θJA≈θJCBOTTOM+

θCB+θBA

⎛

⎝⎜

⎞

⎠⎟ !

θCB+θBA

+θVIA

⎛

⎝⎜

⎞

⎠⎟ (15)

where θJCBOTTOM = 4.0°C/W. The value of θJA = 23°C/W

reported in the Pin Configuration section corresponds to

the demo board.

θJCBOTTOM

θJCTOP

θCA

θCB

θVIA

θBA

PCB

LQFN

PCB

TCTOP

3312SA F06

DIE

PACKAGE

SUBSTRATE

Figure 6. Multi-Layer PCB with Thermal Vias Acts as a Heat Sink

The low value of θJCBOTTOM means that θJA will be

dominated by (θCB + θBA) and θVIA. Minimize θVIA by

including a large number of low thermal resistance vias

from the top layer ground plane to ground plane(s) on

lower levels, close to the exposed paddle of the part.

Minimize (θCB + θBA) by having more ground planes that

are larger, uninterrupted, and higher copper-weight. See

the Application Note, Application Notes for Thermally

Enhanced Leaded Plastic Packages, for the proper size

and layout of the thermal vias and solder stencils. The

maximum load current should be derated as the ambient

temperature approaches the maximum junction rating.

Power dissipation within the LTC3312SA is estimated by

calculating the total power loss from an efficiency mea-

surement and subtracting the inductor loss.

APPLICATIONS INFORMATION

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