ST25R3916 datasheet(61/157 Pages) STMICROELECTRONICS

61 / 157 page

DS12484 Rev 4

61/157

ST25R3916/7

Application information

156

4.4.2

Stop all activities

This direct command stops any ongoing activities:



performs Clear FIFO command



stops data transmission and reception



stops all timers, including FDT timer



clears IRQ line an IRQ status bits



stops Field ON commands

If Stop All Activities is received during RF collision avoidance, the field detection is

terminated and field is not set, consequently no interrupts are sent



stops automatic field ON (same as above)



stops automatic field OFF

If Stop All Activities is received during waiting for automatic field off via GPT, the field

remains on



nfc_ar is set to 01b, then it clears the awareness that there was a previous reception



stops Temporary Enable

This command does not update any register apart from the FIFO status registers. Therefore

it does not disable the field detector in CE mode (if it was enabled), and it does not switch off

the field (if it was enabled).

4.4.3

Clear FIFO

This direct command clears the FIFO and the FIFO status registers. It does not clear the

IRQ line or IRQ status bits.

To prepare a transmission send this command first before writing data into the FIFO. If a

Clear FIFO command is sent during an ongoing data transmission, then the data

transmission is aborted and FIFO and FIFO status registers are cleared.

4.4.4

Transmit commands

The transmit direct commands are used to start a data transmission from the ST25R3916/7.

They switch the device to reception mode after the transmission is completed.

Before sending commands Transmit with CRC and Transmit without CRC, direct command

Clear FIFO has to be sent, followed by the definition of the number of transmitted bytes and

writing data to be transmitted in FIFO.

Use the direct commands Transmit REQA and Transmit WUPA to transmit ISO14443A

short frame commands REQA and WUPA respectively. It is not necessary to send the direct

command Clear FIFO before these two commands.

If the antcl bit is set, then the number of valid bits in the last byte must be set to 0 (nbtx<2:0>

in the Number of transmitted bytes register 2) prior to the direct command Transmit REQA

or Transmit WUPA.

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