ST25R3916 datasheet(72/157 Pages) STMICROELECTRONICS

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Application information

ST25R3916/7

72/157

DS12484 Rev 4

4.5.2

IO configuration register 2

Address: 01h

Type: RW

Table 20. IO configuration register 2

Bit

Name

Default

Function

Comments

sup3V

0: 5 V supply

1: 3.3 V supply

Set to 0 for 3.6 V < VDD ≤ 5.5 V

Set to 1 for 2.4 V ≤ VDD ≤ 3.6 V

vspd_off

0: Enable VDD_D regulator

1: Disable VDD_D regulator

Used for low cost applications. When this

bit is set:

– at 3 V or 5 V supply VDD_D and VDD_A

must be shorted externally

aat_en

0: Disable AAT D/A

1: Enable AAT D/A

The AAT D/A converters are enabled if both

aat_en and en are set. If only aat_en is set

and en is cleared, then the AAT outputs are

set to a fixed value.

Note that for the fixed value to operate, en

must have been set to 1 at least once, prior

to having en = 0.

miso_pd2

1: Pull-down on MISO, when BSS is

low and MISO is not driven by the

ST25R3916/7.

Valid only in SPI mode.

miso_pd1

1: Pull-down on MISO when BSS is

high

io_drv_lvl

0: Normal IO driver level

1: Increase IO driving level

Increases IO driver strength of MISO,

MCU_CLK an IRQ.

Recommended to set to 1 for all I2C

operation, and for SPI operation if

VDD_IO < 3.3 V.

am_ref_rf

0: VDD_AM regulator reference from

VDD_DR

1: VDD_AM regulator reference from

VDD_RF

Selects non modulated RF voltage level

reference of the VDD_AM voltage regulator.

slow_up

1: Slow ramp at Tx on

≥ 10 µs, 10% to 90%, for B

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