STM32L010R8 datasheet(20/92 Pages) STMICROELECTRONICS

Numer części	STM32L010R8

Szczegółowy opis	Value line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0,64-Kbyte Flash memory, 8-Kbyte SRAM, 256-byte EEPROM, ADC

PDF	92 Pages

Scroll/Zoom	100%

Producent	STMICROELECTRONICS [STMicroelectronics]

Strona internetowa	http://www.st.com

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20 / 92 page

Functional overview

STM32L010K8 STM32L010R8

20/92

DS12325 Rev 3

Figure 2. Clock tree

MSv34747V2

Legend:

HSE = High-speed external clock signal

HSI = High-speed internal clock signal

LSI = Low-speed internal clock signal

LSE = Low-speed external clock signal

MSI = Multispeed internal clock signal

Watchdog LS

LSI RC

LSE OSC

RTC

LSI tempo

@V33

/ 1,2,4,8,16

HSI16 RC

Level shifters

HSE OSC

Level shifters

LSU

1 MHz Clock

Detector

LSD

/ 8

LSE tempo

MSI RC

Level shifters

/ 2,4,8,16

/ 2,3,4

Level shifters

PLL

3,4,6,8,12,16,

24,32,48

AHB

PRESC

/ 1,2,…, 512

Clock

Source

Control

@V33

@V18

I2C1CLK

LPUART/

UARTCLK

LPTIMCLK

LSE

HSI16

SYSCLK

PCLK

LSI

not (sleep or

deepsleep)

not (sleep or

deepsleep)

not deepsleep

HCLK

TIMxCLK

CK_PWR

FCLK

PLLCLK

HSE

HSI16

MSI

LSE

LSI

HSE present or not

@V33

@VDDCORE

ck_rchs

/ 1,4

HSI16

MSI

4 MHz

ck_pllin

Enable Watchdog

RTC2 enable

ADC enable

ADCCLK

LSU

LSD

MCO

MCOSEL

PLLSRC

RTCSEL

System

Clock

Peripherals

enable

Peripherals

enable

Peripheral

clock enable

PCLK1 to APB1

peripherals

If (APB1 presc=1) x1

else x2)

to TIMx

Peripheral

clock enable

APB2

PRESC

/ 1,2,4,8,16

Peripheral

clock enable

PCLK2 to APB2

peripherals

32 MHz

max.

If (APB2 presc=1) x1

else x2)

to TIMx

Peripherals

enable

APB1

PRESC

/ 1,2,4,8,16

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