HC705C9AGRSSLASHD datasheet(74/157 Pages) NXP

74 / 157 page

General Release Speciﬁcation

Timer I/O Registers

MC68HC705C9A — Rev. 2.0

Capture/Compare Timer

8.4.4 Alternate Timer Registers (ATRH and ATRL)

The alternate timer registers, shown in Figure 8-5, contain the current

high and low bytes of the 16-bit counter. Reading ATRH before reading

ATRL causes ATRL to be latched until ATRL is read. Reading ATRL has

no effect on the timer overflow flag (TOF). Writing to the alternate timer

registers has no effect.

Figure 8-5. Alternate Timer Registers (ATRH and ATRL)

NOTE:

To prevent interrupts from occurring between readings of ATRH and

ATRL, set the interrupt flag in the condition code register before reading

ATRH, and clear the flag after reading ATRL.

ATRH

$001A

Bit 7

Bit 0

Read:

BIT15

BIT14

BIT13

BIT12

BIT11

BIT10

BIT9

BIT8

Write:

Reset:

11111111

ATRL

$001B

Bit 7

Bit 0

Read:

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

Write:

Reset:

11111100

= Unimplemented

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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