MP8830

13

Rev. 1.00

PIN OUT DEFINITIONS

Pin #

Pin Name

Function

1, 44

Digital positive power supplies. 5 V. Should be decoupled to digital GND plane. The two

internal ADC output data bus drivers.

43, 64

DGND (2)

Digital negative power supplies. 0 V. The two DGND pins both connect to the ESD ring as

well as the control logic and data port logic.

31

24

17

47

Analog positive power supplies. 5 V. Should be star connected to the analog supply post or

the ADC internal logic only.

36

30

23

46

AGND1,

BGND1,

CGND1,

GND3

Analog negative power supplies. 0 V. Should be star connected to analog ground post or

direct connection to the analog ground plane. These GNDs power the analog sections of the

ADC and the circuitry in the DACs. GND3 pin connects to the internal ADC data bus and the

ADC internal logic.

32

28

21

AGND2,

BGND2,

CGND2

Analog grounds related to DAC bias are the common voltage for the reference. The ADC

ladder resistor terminates to this pin as well as the internal bias resistor used for setting the

DAC reference. These pins should be used as the reference ground voltage for all analog

measurements.

52

AENL

Channel A data clock, active low. A DAC data loaded into first register bank on the falling

edge of AENL.

51

BENL

Channel B data clock, active low. B DAC data loaded into the first register on the falling edge

of BENL. B ADC data loaded to the ADC output port on falling edge (and should be read on

the rising edge).

50

CENL

Channel C data clock, active low. C DAC data loaded into the first register on the falling edge

of CENL. C ADC data loaded to the ADC output port on falling edge (and should be read on

the rising edge).

53

CVL

Cycle clock. All DACs loaded on rising edge. Begin sample of analog input on rising edge. A

ADC data is loaded to the ADC output port on the rising edge of CVL (and should be read on

the rising edge of AENL).

48

CREN

Pass through mode enable. When CREN is high, passthrough mode between the ADC and

DAC ports is enabled. RNW controls the direction of pass through operation.

49

RNW

READ not WRITE signal. RNW controls the direction of the pass through operation when

CREN is high and has no impact when CREN is low. When RNW is high data passes from

the DAC port to the ADC port. When RNW is low, data passes from the ADC port to the DAC

port. Note, the port connections are: CD5; AD0; CD6; AD1;......;CD14; AD9.

39

its particular analog input pin.

45

FAST

Fast mode enable. The FAST pin controls the mode of the ADCs. When low, the part func-

tions as specified for 10-bit resolution. When high, the ADC’s resolution becomes 4-bit and

the LSBs are forced low. The clock rate can be increased in this mode to 3 MHz.

37

ACLP

Clamp voltage A. Black level clamp pin for the A channel.

29

BCLP

Clamp voltage B. Black level clamp pin for the B channel.

22

CCLP

Clamp voltage C. Black level clamp pin for the C channel.

41

DCL

Black level clamp control (active low). Black level clamp enable for all pins. All Black level

clamps are turned on when DCL is low.

35

AAN

A channel analog input.

27

BAN

B channel analog input.

20

CAN

C channel analog input.

38

VCAL

Calibration input voltage.