CLRC663 datasheet(28/177 Pages) NXP

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NXP Semiconductors

CLRC663

High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this respect, the

START (S) and repeated START (Sr) conditions are functionally identical. Therefore, the S symbol will be used

as a generic term to represent both the START and repeated START (Sr) conditions.

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START condition

SCL

SDA

SCL

SDA

STOP condition

Figure 18. START and STOP conditions

8.4.4.4 I2C byte format

Each byte has to be followed by an acknowledge bit. Data is transferred with the MSB first, see Figure 18. The

number of transmitted bytes during one data transfer is unrestricted but shall fulfill the read/write cycle format.

8.4.4.5 I2C Acknowledge

An acknowledge at the end of one data byte is mandatory. The acknowledge-related clock pulse is generated

by the master. The transmitter of data, either master or slave, releases the SDA line (HIGH) during the

acknowledge clock pulse. The receiver shall pull down the SDA line during the acknowledge clock pulse so that

it remains stable LOW during the HIGH period of this clock pulse.

The master can then generate either a STOP (P) condition to stop the transfer, or a repeated START (Sr)

condition to start a new transfer.

A master-receiver shall indicate the end of data to the slave- transmitter by not generating an acknowledge on

the last byte that was clocked out by the slave. The slave-transmitter shall release the data line to allow the

master to generate a STOP (P) or repeated START (Sr) condition.

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clock pulse for

acknowledgement

SCL FROM

MASTER

DATA OUTPUT

BY RECEIVERER

DATA OUTPUT

BY TRANSMITTER

acknowledge

START

condition

not acknowledge

Figure 19. Acknowledge on the I2C- bus

CLRC663

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Product data sheet

Rev. 5.3 — 3 January 2024

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