CLRC663 datasheet(12/177 Pages) NXP

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NXP Semiconductors

CLRC663

High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

The bit IdleIRQ in register IRQ0 is set if a command finishes and the content of the command register changes

to idle.

The register WaterLevel defines both - minimum and maximum warning levels - counting from top and from

bottom of the FIFO by a single value.

The bit HiAlertIRQ in register IRQ0 is set to logic 1 if the HiAlert bit is set to logic 1, that means the FIFO data

number has reached the top level as configured by the register WaterLevel and bit WaterLevelExtBit.

The bit LoAlertIRQ in register IRQ0 is set to logic 1 if the LoAlert bit is set to logic 1, that means the FIFO data

number has reached the bottom level as configured by the register WaterLevel.

The bit ErrIRQ in register IRQ0 indicates an error detected by the contactless UART during receive. This is

indicated by any bit set to logic 1 in register Error.

The bit LPCDIRQ in register IRQ0 indicates a card detected.

The bit RxSOFIRQ in register IRQ0 indicates a detection of a SOF or a subcarrier by the contactless UART

during receiving.

The bit GlobalIRQ in register IRQ1 indicates an interrupt occurring at any other interrupt source when enabled.

Interrupt bit

Interrupt source

Is set automatically, when

Timer0IRQ

Timer Unit

the timer register T0 CounterVal underflows

Timer1IRQ

Timer Unit

the timer register T1 CounterVal underflows

Timer2IRQ

Timer Unit

the timer register T2 CounterVal underflows

Timer3IRQ

Timer Unit

the timer register T3 CounterVal underflows

TxIRQ

Transmitter

a transmitted data stream ends

RxIRQ

Receiver

a received data stream ends

IdleIRQ

Command Register

a command execution finishes

HiAlertIRQ

FIFO-buffer pointer

the FIFO data number has reached the top level as configured by the

LoAlertIRQ

FIFO-buffer pointer

the FIFO data number has reached the bottom level as configured by

the register WaterLevel

ErrIRQ

contactless UART

a communication error had been detected

LPCDIRQ

LPCD

a card was detected when in low-power card detection mode

RxSOFIRQ

Receiver

detection of a SOF or a subcarrier

GlobalIRQ

all interrupt sources

will be set if another interrupt request source is set

Table 6. Interrupt sources

8.2 Timer module

Timer module overview

The CLRC663 implements five timers. Four timers -Timer0 to Timer3 - have an input clock that can be

configured by register T(x)Control to be 13.56 MHz, 212 kHz, (derived from the 27.12 MHz quartz) or to

be the underflow event of the fifth Timer (Timer4). Each timer implements a counter register which is 16 bit

wide. A reload value for the counter is defined in a range of 0000h to FFFFh in the registers TxReloadHi and

TxReloadLo. The fifth timer Timer4 is intended to be used as a wake-up timer and is connected to the internal

LFO (Low Frequency Oscillator) as input clock source.

CLRC663

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5.3 — 3 January 2024

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