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AX88796ALF Arkusz danych(PDF) 23 Page - ASIX Electronics Corporation

Numer części AX88796ALF
Szczegółowy opis  10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM
PDF  68 Pages
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Producent  ASIX [ASIX Electronics Corporation]
Strona internetowa  http://www.asix.com.tw
Logo ASIX - ASIX Electronics Corporation

AX88796ALF Arkusz danych(HTML) 23 Page - ASIX Electronics Corporation

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AX88796ALF
3-in-1 Local Bus Fast Ethernet Controller
Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved.
4.1.3 Broadcast Address Match Filter
The Broadcast check logic compares the Destination Address Field (first 6 bytes of the received packet) to all 1’s, which is
the values are “FF FF FF FF FF FF FF” in Hex format. If any bit of the six bytes does not equal to 1’s, the Protocol Control
Logic rejects the packet.
4.1.4 Aggregate Address Filter with Receive Configuration Setup
The final address filter decision depends on the destination address types, identified by the above 3 address
match filters, and the setup of parameters of Receive Configuration Register.
Definitions of address match filter result are as following:
Signal
Value
Description
Phy
=1
Unicast Address Match
=0
Unicast Address not Match
Mul
=1
Multicast Address Match
=0
Multicast Address not Match
Bro
=1
Broadcast Address Match
=0
Broadcast Address not Match
AGG
=1
Aggregate Address Match
=0
Aggregate Address not Match
The meaning of AB, AM and PRO signals, please refer to “Receive Configuration Register”
Aggregate Address Filter function will be:
AGG
Bro
AB
/Bro
/Mul
PRO
/Bro
Mul
AM
Phy
AND
Logic
AND
Logic
AND
Logic
OR
Logic



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