AX88796ALF datasheet(27/68 Pages) ASIX

27 / 68 page

AX88796ALF

3-in-1 Local Bus Fast Ethernet Controller

be done.

END OF PACKET OPERATIONS

At the end of the packet the AX88796A determines whether the received packet is to be accepted or rejected.

It either branch to a routine to store the Buffer Header or to another routine that recovers the buffers used to

store the packet.

SUCCESSFUL RECEPTION

If the packet is successfully received as shown, the DMA is restored to the first buffer used to store the packet

(pointed to by the Current Page Register). The DMA then stores the Receive Status, a Pointer to where the next

packet will be stored and the number of received bytes. Note that the remaining bytes in the last buffer are

discarded and reception of the next packet begins on the next empty 256 byte buffer boundary. The Current

Page Register is then initialized to the next available buffer in the Buffer Ring. (The location of the next buffer

had been previously calculated and temporarily stored in an internal scratchpad register.)

BUFFER RECOVERY FOR REJECTED PACKETS

If the packet is a runt packet or contains CRC or Frame Alignment errors, it is rejected. The buffer

management logic resets the DMA back to the first buffer page used to store the packet (pointed to by CPR),

recovering all buffers that had been used to store the rejected packet. This operation will not be performed if

the AX88796A is programmed to accept either runt packets or packets with CRC or Frame Alignment errors.

The received CRC is always stored in buffer memory after the last byte of received data for the packet.

Error Recovery

If the packet is rejected as shown, the DMA is restored by the AX88796A by reprogramming the DMA starting

address pointed to by the Current Page Register.

AX88796ALF Arkusz danych(PDF) 27 Page - ASIX Electronics Corporation