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PWD5T60 Arkusz danych(PDF) 4 Page - STMicroelectronics |
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PWD5T60 Arkusz danych(HTML) 4 Page - STMicroelectronics |
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4 / 27 page ![]() 3 Electrical data 3.1 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 2 may cause permanent damage to the device. Exposure to maximum rating conditions for extended periods may affect device reliability. All voltages referred to ground (GND) unless otherwise specified. Table 2. Absolute maximum ratings Symbol Parameter Test Condition Min Max Unit VCC Power supply voltage -0.3 21 V VCC-SENSEx VCC to SENSE pin voltage -0.3 25 V VBOx BOOT to OUT pin -0.3 21 V BVDSS MOSFETs blocking Voltage TJ = 25°C 500 V ID Drain current (per MOSFET) DC @TCB = 25 °C (1) 3.5 A DC @TCB = 100 °C (1) (2) 2 A Pulse @TCB = 25 °C (1) (2) (3) 14 A SROUT Full bridge outputs slew rate (10% - 90%) (2) 40 V/ns VOUTx Output voltage VBOOTx - 21 500 V VBOOTx Bootstrap voltage -0.3 520 V VCIN Comparator input voltage -0.3 20 V Vi Logic input voltage (4) - 0.3 15 V VOD Open-drain voltage (OD, FAULT) -0.3 21 V VFAULT FAULT pin voltage - 0.3 21 V VISO Isolation Voltage (1 min) (2) 2500 VRMS TJ Junction temperature -40 125 °C Tstg Storage temperature -50 150 °C PTOT Total power dissipation (5) Tamb = 25°C JEDEC board (6) (7) 5.2 W ESD Human Body Model 2 (8) kV 1. TCB is the temperature of the case-bottom pad. 2. Not tested in production. 3. The value specified by the pulse duration limited by maximum junction temperature. 4. EN, LINx and HINx pins. 5. Value calculated basing on thermal resistance, power uniformity distributed over the six power MOSFETs, still air. 6. The device mounted on a FR4 2s2p board as JESD51-5/7. 7. Actual applicative board max. dissipation could be higher or lower depending on the layout and cooling techniques. 8. Pins 12, 13, 14, 15, 20 and 21 have HBM ESD value ± 1.75 kV PWD5T60 Electrical data DS14558 - Rev 2 page 4/27 |
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