LT7184S datasheet(30/52 Pages) AD

30 / 52 page

Data Sheet

LT7184S

analog.com

Rev. 0

30 of 52

the PWM output by the value set in MFR_PWM_PHASE_LT7184S command. Only one device connected to SYNC

may be configured as an output. When a clock is applied to SYNC, the MFR_PWM_PHASE_LT7184S command

specifies the phase relationship between the rising edge of SYNC and the rising edge of SW for the channel.

The switching frequency of each channel of the LT7184S may be independently programmed to double the SYNC

clock frequency or the FREQUENCY_SWITCH frequency by setting bit 15 of the MFR_PWM_MODE_LT7184S to 1. To

prevent the switching frequency from exceeding 4MHz when bit 15 is set to 1, the FREQUENCY_SWITCH command

is limited to 2MHz. If the FREQUENCY_SWITCH command is set to a value greater than 2MHz, then the user is

prevented from setting Bit 15 to 1. When programming the 2x switching frequency, do not apply a clock with a

frequency of more than 2MHz to the SYNC pin.

Table 9. PWM_CFG Pin Configuration Resistor Selection8

RESISTOR

VALUE

(±1%)

PWM

FREQUENCY1,2

PWM PHASE3

POLYPHASE

FOLLOWER/

LEADER4

INTERNAL COMPENSATION5

SYNC

CLOCK

OUTPUT

or INPUT7

CH0

CH1

CITH

RITH

gMEA

Floating or

VDD18

Initialized from

NVM

(default 1MHz)

Initialized

from NVM

(default

0°)

Initialized

from NVM

(default

180°)

Initialized

from NVM

(default 0

Leader)

Initialized

from NVM

(default

165pF)

Initialized

from NVM

(default

14kΩ)

Initialized

from NVM

(default

310μS)

Initialized

from NVM

(default

Input)

124kΩ

500kHz

0°

180°

0 (Leader)

165pF

60kΩ

155μs

0 (Input)

80.6kΩ

1.5MHz

145pF

10kΩ

465μs

51.1kΩ

2MHz

145pF

10kΩ

465μs

30.9kΩ

4MHz

95pF

10kΩ

930μs

107kΩ

500kHz

90°

270°

165pF

60kΩ

155μs

69.8kΩ

1MHz

165pF

14kΩ

310μs

43.2kΩ

2MHz

145pF

10kΩ

465μs

5.6KΩ

±10%

PolyPhase configuration: PWM Configuration is controlled by the VOUT1_CFGpin, as shown in Table 10. In this

configuration, VOUT for both channels is initialized to the value specified by the VOUT0_CFGresistor.

PWM Switching frequency set point is controlled by the FREQUENCY_SWITCH command if no SYNC clock is

present.

In an external synchronization clock, as well as a configuration resistor, the configuration resistor should be

chosen to set the internal PWM switching frequency to a similar value as the input clock frequency.

Steady-state PWM switching phase is controlled by MFR_PWM_PHASE_LT7184S.

POLYPHASE® follower/leader mode is controlled by MFR_CHAN_CONFIG_LT7184S bit 8. A value of 1 selects

follower mode.

Internal compensation is selected by connecting the ITH pin to INTVCC. For PWM_CFG resistor values ≤ 124kΩ, if

external compensation is used, gMEA is set to the maximum value (5.0ms for high-performance low-VOUT Mode;

1.24ms for standard mode). For internal compensation, CITH is controlled by MFR_PWM_MODE_LT7184S bits [8:6],

RITH is controlled by MFR_PWM_MODE_LT7184S bits [5:3], and gMEA is controlled by MFR_PWM_MODE_LT7184S Bits

[13:11]. When the NVM configuration selects high-performance Low VOUT mode, the error amp transconductance

(gMEA) is multiplied by about 4.

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