LT7184S datasheet(14/52 Pages) AD

14 / 52 page

Data Sheet

LT7184S

analog.com

Rev. 0

14 of 52

Name

DESCRIPTION

VSENSE1N

Output voltage negative sense input. Connect to the Channel 1 output voltage sense

ground point.

VSENSE1P

Output voltage positive sense input. Connect to the Channel 1 output voltage sense

point.

Write protect pin. When this pin is high, only the PAGE, OPERATION, MFR_EE_UNLOCK,

and CLEAR_FAULTS commands are write-able. Clear individual fault bits by writing a 1

to the respective bits in the STATUS commands.

VOUT1_CFG

Output voltage configuration for Channel 1 or poly phase configuration. If the PWM_CFG

pin is NOT configured for PolyPhase, the 1% resistor from VOUT1_CFG to the ground (either

SGND or PGND) will be selected as the voltage set point according to Table 7 in the

Applications Information section. If the PWM_CFG pin is configured for poly phase

operation, then the Channel 1 output is set to the same value as Channel 0 based on

VOUT0_CFG, and a 1% resistor from VOUT1_CFG to ground selects a PolyPhase configuration

according to Table 10 in the Applications Information section. The VOUT1_CFG pin is read at

LT7184S start-up.

EXTVCC

Optional Power Supply input. If connected to 3V to 5.5V, this pin is used to derive the

DRVCC, INTVCC, and VDD18 supplies. If one of the regulator outputs is set to output 3V or

greater, that output may be connected to EXTVCC to reduce power loss. If this pin is not

connected to a regulator output, apply a 0.1µF or greater local bypass capacitor on this

pin to GND as close as possible to the LT7184S.

RUN0

Channel 0 Regulator Enable Input. Logic high enables the Channel 0 regulator. The RUN0

pin is pulled down with 1.5mA (typical) during POR and reset to facilitate sequencing

with other regulators but may be over-driven high by a digital output of another device.

This pin may be connected directly to DRVCC to enable the regulator when input power

is present.

RUN1

Channel 1 Regulator Enable Input. Logic high enables the Channel 1 regulator. The RUN0

pin is pulled down with 1.5mA (typical) during POR and reset to facilitate sequencing

with other regulators but may be over-driven high by a digital output of another device.

This pin may be tied directly to DRVCC to enable the regulator when input power is

present.

SHARE_CLK

Bidirectional Open-Drain Sequence Time Base Share Clock. Nominally 100kHz. Used to

align start-up and shutdown of regulator outputs among multiple Analog Devices’

products when PolyPhase or time-based sequencing is employed. A pull-up resistor to

1.6V to 5.5V is required if SHARE_CLK is connected between multiple devices to

synchronize sequencing. If time-based sequencing is not used, leave the SHARE_CLK pin

floating. It is pulled up to VDD18 inside the chip through a diode and a 100kΩ resistor.

FAULT1

Input/Open-Drain Output. The LT7184S pulls the FAULT1 pin down with 1.5mA (typical)

when an unmasked fault occurs on the Channel 1 regulator. If another device pulls down

the FAULT1 pin, the LT7184 Channel 1 regulator turns off immediately. If PolyPhase

configuration is used, tie together the FAULTN pins of all PolyPhase channels. If

the PolyPhase configuration is used, or if FAULTN pin reporting or sharing is required,

a pull-up resistor of 6.8kΩ or greater to 1.6V to 5.5V is required. FAULT1 pin may be

connected directly to DRVCC if the FAULT1 pin function is not required.

FAULT0

Input/Open-Drain Output. The LT7184S pulls the FAULT0 pin down with 1.5mA

(typical) when an unmasked fault occurs on the Channel 0 regulator. If another device

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