LT7184S datasheet(32/52 Pages) AD

32 / 52 page

Data Sheet

LT7184S

analog.com

Rev. 0

32 of 52

Table 10. PolyPhase Operation VOUT1_CFG Pin Configuration Resistor Selection

RESISTOR

VALUE

(±1%)1

PWM

FREQUENCY2

PWM PHASE3

POLYPHASE®

FOLLOWER4

SYNC CLOCK:

OUTPUT / INPUT5

CH0

CH1

CH0

CH1

Floating or

VDD18

Initialized

from NVM

(default 1MHz)

Initialized

from NVM

(default 0°)

Initialized

from NVM

(default 180°)

Initialized from NVM

(default 0, leader)

Initialized from

NVM

(default 0, input)

124kΩ

500kHz

0°

180°

(leader)

(follower)

(output)

80.6kΩ

1MHz

36.5kΩ

2MHz

16.5kΩ

4MHz

107kΩ

500kHz

(input)

69.8kΩ

1MHz

30.9kΩ

2MHz

11.8kΩ

4MHz

93.1kΩ

500kHz

90°

270°

(follower)

60.4kΩ

1MHz

25.5kΩ

2MHz

6.65kΩ

4MHz

51.1kΩ

1MHz

120°

240°

(output)

21.0kΩ

2MHz

43.2kΩ

1MHz

60°

300°

(input)

0kΩ (GND)

2MHz

Table 10 applies only if PWM_CFG is connected to a 5.6kΩ configuration resistor. Otherwise, VOUT1_CFG controls the

output voltage for Channel 1 according to Table 7.

PWM switching frequency is controlled by the FREQUENCY_SWITCH and MFR_PWM_MODE_ LT7184S Bit 15, if no

SYNC input clock is present.

Steady-state PWM switching phase is controlled by MFR_PWM_PHASE_LT7184S.

POLYPHASE® follower mode is controlled by MFR_CHAN_CONFIG_LT7184S bit 8. A value of 1 selects follower mode,

and a value of 0 selects leader mode. Exactly one channel must be selected as a leader.

The SYNC pin is a clock output when MFR_SYNC_CONFIG_LT7184S bit 0 is set to 1.

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