LT7184S datasheet(23/52 Pages) AD

23 / 52 page

Data Sheet

LT7184S

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Rev. 0

23 of 52

Switching Regulator Control Loop

The LT7184S employs a controlled, on-time, valley current mode architecture. In normal operation, the internal top

power Metal-oxide-semiconductor FET (MOSFET) is turned on for an interval determined by an on-time control

circuit. When the top power MOSFET turns off, the bottom power MOSFET turns on until the valley current

comparator trips, restarting the on-time control circuit and initiating the next cycle. The inductor current is

determined by sensing the voltage drop across the bottom power MOSFET when it is on. The voltage on the ITHN pin

sets the comparator threshold corresponding to the inductor valley current. The error amplifier (EA) adjusts the ITH

voltage by comparing the output voltage with an internal reference Digital-to-analog Converter (DAC) output. If the

load current increases, the output voltage drops relative to the internal reference, which causes the ITH voltage to

rise until the average inductor current matches that of the load current.

An internal phase-locked loop synchronizes the oscillator frequency to an external clock signal if one is present on

the SYNC pin. If no external clock is applied, the switching frequency is set by the FREQUENCY_SWITCH command,

which may be initialized using configuration resistors (see the Applications Information section for more details).

Soft-Start

The LT7184S has two Pulse Width Modulation (PWM) modes of operation: Pulse-skip mode (PSM) and Forced

continuous mode (FCM). Pulse-skip mode is only used during soft-start while the output voltage rises to the

programmed regulation voltage. During PSM or discontinuous operation, the inductor current cannot be reversed.

The reverse current comparator turns off the bottom switch when the inductor current reaches zero, preventing the

inductor current from going negative and discharging the output. During discontinuous operation, the power

MOSFETs remain off while the output capacitor supplies the load current. The LT7184S switches again when the ITH

voltage rises above the zero current level to initiate the next cycle as either the internal reference voltage rises above

the VSENSEvoltage with the soft-start ramp, or the load discharges the VSENSE voltage.

When all conditions required for startup have been met, and a channel is enabled with an OPERATION command or

when the RUN pin is raised, a soft-start ramp begins. The soft-start ramp time is set by the TON_RISE command,

which is 1ms by default. The soft start ramp begins after a programmable delay (TON_DELAY, default 0ms). Once the

output voltage reaches the programmed regulation voltage (VOUT_COMMAND), the PGOOD flag is set, and the

operating mode automatically switches to the FCM mode of operation.

FCM mode – where the inductor always conducts current, reversing below zero for some portion of the switching

cycle when the average output current is below the ripple current and either the top or bottom power MOSFETs are

always on - is also called as Continuous conduction mode (CCM). In this constant on-time current mode control

architecture, the inductor valley current is always determined by the voltage on the ITH node. The ITH node voltage

varies from about 0.6V to 1.5V depending on the load, with the zero load current when the ITH voltage is about 980mV.

When programmed to use internal compensation (ITH pin connected to INTVCC), the ITH node is not visible on the ITHN

pin. When a compensation network is connected to the ITHN pin at startup, the LT7184S uses the user-supplied

compensation to control the loop dynamics. Care must be used in selecting compensation network components for

correct operation.

EEPROM

The LT7184S contains internal EEPROM to store nonvolatile user configuration settings and fault log information.

The integrity of the onboard EEPROM is protected with ECC and checked with a cyclic redundancy check (CRC)

calculation after a power-on, reset, or execution of a RESTORE_USER_ALL command. If an invalid CRC is detected,

the ALERT, SHARE_CLK, PGOOD, and RUN pins are pulled low, and both output channels remain disabled until the

issue is resolved.

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