S25FL256SDPNFAQ datasheet(114/149 Pages) CYPRESS

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Document Number: 001-98283 Rev. *M

Page 113 of 148

S25FL128S/S25FL256S

9.8.2

ASP Program (ASPP 2Fh)

Before the ASP Program (ASPP) command can be accepted by the device, a Write Enable (WREN) command must be issued. After

the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch (WEL) in the Status Register to

enable any write operations.

The ASPP command is entered by driving CS# to the logic low state, followed by the instruction and two data bytes on SI, least

significant byte first. The ASP Register is two data bytes in length.

The ASPP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same manner as any other

programming operation.

CS# input must be driven to the logic high state after the sixteenth bit of data has been latched in. If not, the ASPP command is not

executed. As soon as CS# is driven to the logic high state, the self-timed ASPP operation is initiated. While the ASPP operation is in

progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a

1 during the self-timed ASPP operation, and is a 0 when it is completed. When the ASPP operation is completed, the Write Enable

Latch (WEL) is set to a 0.

Figure 9.38 ASPP Command

9.8.3

DYB Read (DYBRD E0h)

The instruction E0h is latched into SI by the rising edge of the SCK signal. Followed by the 32-bit address selecting location zero

within the desired sector (note, the high order address bits not used by a particular density device must be zero). Then the 8-bit DYB

access register contents are shifted out on the serial output SO. Each bit is shifted out at the SCK frequency by the falling edge of

the SCK signal. It is possible to read the same DYB access register continuously by providing multiples of eight clock cycles. The

address of the DYB register does not increment so this is not a means to read the entire DYB array. Each location must be read with

a separate DYB Read command. The maximum operating clock frequency for READ command is 133 MHz.

Figure 78. DYBRD Command Sequence

Instruction

SCK

MSB

High Impedance

CS#

MSB

210

039

Instruction

32-Bit

Address

DATA OUT 1

SCK

MSB

High Impedance

CS#

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