S25FL256SDPNFAQ datasheet(117/149 Pages) CYPRESS

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Document Number: 001-98283 Rev. *M

Page 116 of 148

S25FL128S/S25FL256S

9.8.8

PPB Lock Bit Read (PLBRD A7h)

The PPB Lock Bit Read (PLBRD) command allows the PPB Lock Register contents to be read out of SO. It is possible to read the

PPB lock register continuously by providing multiples of eight clock cycles. The PPB Lock Register contents may only be read when

the device is in standby state with no other operation in progress. It is recommended to check the Write-In Progress (WIP) bit of the

Status Register before issuing a new command to the device.

Figure 9.39 PPB Lock Register Read Command Sequence

9.8.9

PPB Lock Bit Write (PLBWR A6h)

The PPB Lock Bit Write (PLBWR) command clears the PPB Lock Register to zero. Before the PLBWR command can be accepted

by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch

(WEL) in the Status Register to enable any write operations.

The PLBWR command is entered by driving CS# to the logic low state, followed by the instruction.

CS# must be driven to the logic high state after the eighth bit of instruction has been latched in. If not, the PLBWR command is not

executed. As soon as CS# is driven to the logic high state, the self-timed PLBWR operation is initiated. While the PLBWR operation

is in progress, the Status Register may still be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress

(WIP) bit is a 1 during the self-timed PLBWR operation, and is a 0 when it is completed. When the PLBWR operation is completed,

the Write Enable Latch (WEL) is set to a 0. The maximum clock frequency for the PLBWR command is 133 MHz.

Figure 83. PPB Lock Bit Write Command Sequence

9.8.10 Password Read (PASSRD E7h)

The correct password value may be read only after it is programmed and before the Password Mode has been selected by

programming the Password Protection Mode bit to 0 in the ASP Register (ASP[2]). After the Password Protection Mode is selected

the PASSRD command is ignored.

The PASSRD command is shifted into SI. Then the 64-bit Password is shifted out on the serial output SO, least significant byte first,

most significant bit of each byte first. Each bit is shifted out at the SCK frequency by the falling edge of the SCK signal. It is possible

to read the Password continuously by providing multiples of 64 clock cycles. The maximum operating clock frequency for the

PASSRD command is 133 MHz.

Figure 84. Password Read Command Sequence

CS#

SCK

Phase

Instruction

Repeat Register Read

Instruction

SCK

High Impedance

CS#

MSB

210

Instruction

SCK

High Impedance

MSB

Password Least Sig. Byte First

MSB

CS#

MSB

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